Over the last two months, I have had several clients approach me for help regarding DDR3 / DDR3L interfaces that they have connected to Xilinx FPGAs. These projects ranged from just starting a design to having a prototype / early production board and realizing that the DDR3 doesn’t function correctly. All these projects used traditional FPGAs from the UltraScale and 7 Series device families.
With that in mind, I thought it would be beneficial to discuss what to consider at the planning, hardware, and FPGA level in order to successfully implement a DDR3/4 interface. Of course, we don’t want to just jump in and create schematics or FPGA designs when working with DDR3/ DDR4 and UltraScale and 7 Series devices. It’s important to read the most applicable application notes and design guides which include the following:
Once you have read the appropriate documentation, you should be able to begin the set up for a simple memory architecture. For example, how many devices are you using, what are your termination requirements (only data has on-chip termination), and how are reference voltages for VTT and VREF provided. If you are really pushing the device performance, then using an external regulator that can provide VTT and VREF is the most sensible idea. Alternatively, lower performance interfaces can use resistor dividers to create the required voltages.
With this understood, you can start creating schematics because you have the necessary information about the required components etc. This is also the time when you can create a simple project in Vivado in your target device to verify the pin out of your DDR3/4 interface.
If we are using the Xilinx 7 Series DDR3 MIG we verify the pin out in the MIG IP block, it is critical to make sure pin out validates before the proceeding with layout.
If the device is an UltraScale part, the IO planning is performed using IO planning in the elaborated or synthesised view. In this view, we can use the bank / byte planner to verify the bank allocation expected for the design.
In the layout stage, we must also be careful to ensure that pin swapping to ease routing does not inadvertently introduce any violations.
Once we are happy with the pin allocation, we can complete the schematics and start the layout. Of course, the layout is the most critical element of the design success. To ensure a successful layout, we must have several explicit and detailed placement and routing constraints. This ranges from the location of the termination resistors, organization of chips on the board, board stack up and routing which define the controlled impedance, and tracking alignment and length matching.
The end outcome of the layout is a fully routed board. However, before the board is sent to manufacture, the design should be subjected to signal integrity and power integrity analysis. Failing to do this will mean there is significant technical risk going forward with the board bring up.
As we bring up the board, the UltraScale and UltraScale+ families provide the developer with a little more information than the 7 Series. Connecting the hardware to the Vivado hardware manager and downloading the Bit file will provide access to the MIG.
Accessing the hardware manager in the MIG will allow us to verify the calibration and timing for each of the byte groups. This hardware manager also provides information on the status of the DDR calibration.
This includes any warnings that might have been generated in the calibration process.
It also includes information regarding the configuration of the MIG in operation.
Hopefully following these steps will reduce the technical risk in your DDR3/4 implementations and significantly reduce stress and the number of hours needed during board commissioning.
Up Coming Book!
Do you want to know more about designing embedded systems from scratch? Check out our upcoming book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design.
We designed and manufactured the board at the heart of the book.
All schematics and layout will be made available on a new website soon!