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MicroZed Chronicles: Design Reuse in IP Integrator

One project we have in the pipeline involves the need to transfer data from one FPGA to another over a fibre link with minimal delay. Like many applications, this will be cost-sensitive, so the target will be an Artix-7 FPGA, as its GTP transceivers provide data rates of up to 6.6 Gbps, which is more than sufficient bandwidth.


This application is simple, requiring only a transmit path from one FPGA and a receive path in another. As such, my idea is to use streaming Aurora simplex configurations: one Tx and one Rx. What I needed to know was the time taken from when two bytes enter the Aurora TX module to when they are received by the Aurora RX module and output on its AXI Stream.


Therefore, I wanted to create a project that enabled me to simulate the end-to-end delays of the Tx and Rx. But I also wanted to be able to reuse what I created in the separate FPGA designs. This is where Block Design Containers (BDCs) come in.


If you are not familiar with Block Design Containers, they enable us to segment IP Integrator designs using a more modular approach. We can, of course, use hierarchical blocks in an IP Integrator block diagram; however, while effective, this hierarchy does not enable a team-based design flow. Using a BDC does, as it is essentially an IP Integrator block diagram that is instantiated within another.


This means we can have several engineers developing different BDs, just as we would for an RTL development.


BDCs also have the potential to be turned into a reconfigurable partition that can be used within a DFX flow.


We can develop a BDC using one of two approaches: top-down or bottom-up. In the top-down approach, we develop the IP Integrator design as normal and create levels of hierarchy as desired. We can then turn the hierarchical blocks into a BDC.


The bottom-up approach occurs when we develop several IP Integrator block diagrams separately. These can then be added to a common project and used to create the overall design using BDCs. In this instance, BDCs are created by simply dragging and dropping the separate BDs onto the IP Integrator block diagram.


A BDC flow is exactly what I needed, as it enables me to create TX and RX BDCs that can be used for this project and then reused in the separate projects for the two FPGAs.


As such, I created two block diagrams. The first instantiated an Aurora simplex TX core, while the second implemented an RX core.

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In each block diagram, I added the necessary control and configuration elements and made the required interfaces for clocking, reset, and AXI Streaming external.

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For the TX BDC, I created a simple RTL counter module that outputs its value over AXI Stream. This enables me to transmit a count over the Aurora link. It also means I can easily detect the count at the receiver and determine the time taken for transmission.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity axis_counter is
  generic (
    DATA_WIDTH : positive := 16
  );
  port (
    aclk          : in  std_logic;

    -- AXI-Stream master
    m_axis_tvalid : out std_logic;
    m_axis_tdata  : out std_logic_vector(DATA_WIDTH-1 downto 0);
    m_axis_tready : in  std_logic;
    m_axis_tlast  : out std_logic  -- not used; held low
  );
end entity axis_counter;

architecture rtl of axis_counter is
  -- Power-up initialization 
  signal count_q : unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
  signal m_axis_tvalid_int : std_logic;
begin
  -- Data is always a valid representation of the current count
  m_axis_tdata  <= std_logic_vector(count_q);
  m_axis_tvalid_int <= '1';
  m_axis_tlast  <= '0';
  m_axis_tvalid <= m_axis_tvalid_int;
  
  process (aclk)
  begin
    if rising_edge(aclk) then
      -- Increment on a successful AXI-Stream transfer
      if (m_axis_tvalid_int = '1') and (m_axis_tready = '1') then
        count_q <= count_q + 1;  
      end if;
    end if;
  end process;
end architecture rtl;

The top level of the design looks as shown below. To enable differences in simulation, I used different GT reference clock frequencies.


Looking at the top level, you can see the blue pyramid symbol in the middle of each block, which identifies it as a BDC.

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Running the simulation of this design shows the time to transmit from the AXI Stream TX input to the AXI Stream RX output is about 100 ns. Of course, this does not account for clock compensation periods, etc., but it does give me a ballpark figure (with margin added) that I can use to assign a budget to the project and determine its feasibility. Using the BDC also means I can reuse the Tx and Rx in the hardware prototype when we get the boards in for testing.

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