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MicroZed Chronicles: Alveo Edition, Introducing the Alveo V80

In this blog series, we have looked at several AMD Versal devices from the Prime (VMK180) and AI Core series (VK190) to the AI Edge (TE0905 and VD100) range. In this blog, we are going to examine not only a Versal HBM device but also a new Alveo card, the V80, which is built around the capabilities of the Versal HBM device.

Let's start our journey with an examination of the V80's interfaces and form factor. Interface-wise, the V80 provides developers with:

  • Two PCIe® Gen5 x8 interfaces or one PCIe® Gen4 x16 interface

  • Four QSFP56 ports – These enable each QSFP56 port to support either two 100G links or four links operating at 50/40/25-10G

  • Three MCIO interfaces – These Mini Cool Edge IO interfaces enable fly-over connections of high-speed signals, such as PCIe5, to provide expansion within the server


At the heart of the V80 is the Versal HBM device, the XCV80. This offers developers not only dual-core A72 and R5 processors, but also 2.6 million logic cells, along with two 16GB HBM2e memories interconnected by a network on chip (NoC).

To support application developments, the Alveo V80 also provides 8GB of DDR4 with an expansion slot capable of supporting 32GB of DDR4 via a DIMM slot. Within AMD Versal devices, DDR is a system resource managed by the DDR Memory Controller (DDRMC) within the NoC.

The capabilities of the V80 mean it is ideal for memory-bound compute applications. These applications include genomics, astrophysics, and, of course, networking, such as packet monitoring, cybersecurity, and offloading computational storage, enabling CPU offload.

When it comes to developing applications for the V80, we can leverage Vivado to create implementation. Over the next few blogs, we are going to examine in depth the base design that comes with the V80 to support application development using the Vivado flow.

The architecture of the V80 card provides the PCIe host card interface using the Coherent PCIe Module (CPM) within the Versal Control Interface Processing System (CIPS). Access to the HBM memory is provided by the Versal NoC, which, like the 4GB of DDR4 or 32GB of DDR4 expansion DIMM, makes it a system resource accessible by the CPM or the programmable logic. To support the high bandwidths necessary on these interfaces, the Versal NoC is typically clocked at 1GHz.

It is within the programmable logic that users' applications are able to access the QSFP56 interfaces, leveraging four groups of four GTM transceivers. The dual x4 MCIO and single x8 MCIO interfaces are also implemented by the programmable logic interface.

To support out-of-band signal interfacing, SMBus is used. This interface is implemented within the programmable logic. This provides control over clocking and reset and connects to the RPU R5s, which implement the satellite controller within the V80 Alveo card.

In the next blog, we will take a deep dive into recreating the Alveo Versal Example Design using Vivado.

Workshops and Webinars

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by AMD



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