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Model-based engineering enables engineers to cut down development times by a factor of 5 while maintaining the highest levels of quality.

One of the great features about the new Avnet ZU1CG board is the interfacing it provides. It gives us three SYZYGY interfaces along with...

One of my passions is sharing information about how we can develop better, more effective FPGA designs. This passion is the driving force...

A few months ago, we looked at the AXI Stream FIFO. The AXI Steaming FIFO allows developers to be able to access AXI Streams from AXI...

Announcing 3 new FPGA development-related courses, including a basics course targeted at new graduates or entry-level engineers.

Over the last few weeks, I have been working on commissioning the Nexus Certus™-NX LFD2NX-40 development board. You can find a previous...

It is always exciting when new devices are introduced, and this week, AMD Xilinx announced two new devices into the already popular...

It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to...

Last week we examined the Video Frame Buffer Write (VFBW), which is capable of writing image frames to an external memory. This week, we...

When I’ve previously created image processing blogs or applications, I have tended to use the Video Direct Memory Access (VDMA) module to...

The announcement earlier this year on the collaboration between CAES and Lattice Semiconductor on the availability of space grade...

A few days ago, I noticed that AMD Xilinx had published a blog stating that 7 series devices would be available beyond 2035. I must admit...

On my journey exploring how Cocotb works on a range of interfaces, this week I am going to look at how we can work with AXI Lite and...

A few weeks ago, we looked at how we could build the hardware element of our Nios V processor using Quartus Prime and Platform Designer....

Over the last few weeks, I have been creating a course centered around the Avnet ZUBoard which will be like the MiniZed and Ultra96-V2...

A few weeks ago, we looked at the python-based cocotb framework. In that blog, we looked at a simple memory scrubber created around a XPM...

In our last blog, we looked at the new Nios V soft-core processor for use in our Intel FPGAs. In this blog, we are going to explore how...

Ever since the previous overview, I’ve had the Avnet ZUBoard 1CG sitting on my desk. I also just purchased a FLIR C5 thermal imaging...

Verification of both the modules and top-level testing is often more complex and time consuming than creating the HDL. Previously, we’ve...

A few weeks ago, we talked about how we could synchronise between clock domains in Vivado , I also noticed a couple of questions on...