The announcement earlier this year on the collaboration between CAES and Lattice Semiconductor on the availability of space grade Certus™-NX-RT and CertusPro™-NX-RT FPGAs was of great interest to Adiuvo Engineering and Training ltd.
Collaborating with Anaporia and Rachellie, we have recently created a development / prototyping board based around the Certus™-NX LFD2NX-40 which is commercial equivalent of the Certus-NX-RT device.
This development board has been developed with space applications in mind, particularly command, control, instrumentation, and communication / interfacing. As space missions are required to support a range of applications the development board has most of the IO broken out to headers or Pmod interfaces. This enables the developers to prototype solutions with the use of either off the shelf Pmod e.g CAN, RS485, UART etc or bespoke interfaces such as 1553 or SpaceWire. This approach provides the maximum flexibility, as additional interfaces can also be used on these Pmod interfaces for example image sensors for monitoring cameras, Sensors, ADC or DAC interfaces which can be used for more instrumentation and control applications.
The development board provides the user with the following Resources
80 IO accessible via PMOD
14 ADC Channels – Including ADC Reference
128 Mbit NOR flash for configuration
256 Kbit MRAM memory
100 MHz Oscillator
156.25 MHz Oscillator for the SFP
Lattice In-System Programmable Hardware Management Expander
This architecture provides a very flexible platform, one unique feature is the implementation of the RPI Pico which is connected to the both the FPGA and the In System Programmable Hardware manager. This enables the RPI Pico to access and report telemetry on the supply rails to the FPGA enabling the FPGA current draw to be characterised and easily reported to a monitoring computer. More than that however the RPI Pico can be used to implement and simulate satellite platform, and equipment interfaces enabling hard to create corner cases to be recreated with ease using the programmable state machines.
At the heart of the development board is the Lattice Certus™-NX FPGA which provides the user with 40K LUTs, 2.5 Mbit of BRAM, 56 DSP, 2 ADC and inbuilt 32KHz and 450 MHz Oscillators. This makes it ideal for applications such as deployment cameras, instrumentation, configuration, and control. The power efficiency of the FPGA makes it ideal for use on satellites which are often very power constrained.
Take an example of a deployment camera, a simple CMOS imager can be connected to the FPGA, the FPGA can configure the Imager settings over the camera communications interface e.g. I2C and receive the image information. This image information could be compressed or directly passed a central processing unit using an interface such as SpaceWire etc.
Another example application would be protocol conversion from perhaps ethernet to SpaceWire on a new space application.
A final application could be the thermal control and monitoring, application in this configuration a RISC V processor implemented in the FPGA could be used under Space Wire control to interface with a range of ADC interfaces which measure the temperature at locations in the satellite. These temperatures could be report back to the platform manager, if temperature stability is required, the FPGA could calculate a temperature drive required using a PID algorithm implemented within the FPGA logic.
The CAES space FPGA collaboration with Lattice offers an interesting range of advantages for space applications due to the low power and radiation tolerance, they are also in a very small footprint enabling better SaWP-C solutions.
The Adiuvo Space development board provides developers the ability to rapidly prototype the solution being developed reducing technical risk and increasing the all important Technology Readiness Level.
If you are interested in this development board, contact firstname.lastname@example.org