Lattice Propel RISC-V, part one Hardware

Over the last few weeks, I have been working on commissioning the Nexus Certus™-NX LFD2NX-40 development board. You can find a previous blog on an overview of the board here.

However, it thought it would be good to document a little about some of the projects I have been using to demonstrate the board is working as intended. For the first project I used a simple shift register / counter approach to toggle LEDs on Pmods attached to ensure all the IO was accessible.

The more interesting design however is the one I am going to document here and that it is the implementation of a RISC V processor in the LFD2N-40. This processor will be running from the internally oscillator, toggling the LEDS attached to a PMod and communicating over a USB UART Pmod.

To get started with this we need the following software installed on our development machine

  1. Lattice Radiant – Project Management, Synthesis, Implementation and Simulation

  2. Lattice Propel – System Capture and Software development

These tools can be downloaded from the Lattice Semiconductor website, for the device in question for this board there are no licensing requirements.

To get started with this we are going to start with Propel builder which is where we define the architecture of our processing solution. Propel Builder is very IP based and allows us to create RISC-V based processors solutions. Coupled with a range of RISC-V processors, is a range of IP to provide interfacing, memories, and internal interconnects. The three processors provided are

  1. RISC-V SM RV32I, five stage pipeline and integral timer and Interrupt controller. The RISC-V SM provides 0.5 DMIPS/MHz

  2. RISC-V MC RV32IC, five stage pipeline with integral timer and interrupt controller along with instruction and data cache. The RISC-V MC provides 0.7 DMIPS/MHz

  3. RISC-V RX RV32IMC, five stage pipeline with integral timer, interrupt controller, caches, and tightly coupled memories. The RISC-V RX can provide 1.01DMIPS/MHz

For this application I am going to implement a RISC-V MC, once propel builder opens, we need to create a new design. This is available from the File menu and doing so will open a wizard which enabled us to define the project location and project name.

The next step is to then define the target processor, the desired processor type, and the operating conditions. Here you get the option to decide either to have an empty project or a typical hello world project. For this example, I selected the hello world project.

Once this is completed you will see the summary page, click finish and the project will be opened.

This will open a visible representation of the system, in that system you will see the RISC-V processor, UART, GPIO, System Memory and the necessary APB Interconnects and Bridges. The clocking for the design is provided by the on-chip oscillator, this provides two outputs a high frequency output at 450 MHz and low frequency output at 128 KHz. The high frequency output is enabled and set to a frequency of 112.5 MHz. The oscillator feeds a PLL which generates two outputs the main clock at 50MHz and a secondary output at 28.125MHz.

The processor configuration can also be modified if required, for example if the caches are desired.

With the basics of the design ready the next stage is to validate the design using the button on the menu bar. Once validated the design RTL can be generated again using the generate button on the menu bar. This will generate the RTL which can be implemented in Radiant.

If we want to see the address map of the system, we can click on the address tab.

The next step once the RTL has been generated is to open radiant to implement the design. Clicking on the radiant button on the menu will open a radiant project properly configured for implementation all we have to do is assign the IO to the desired board locations.

Once Radiant opens we are then able to assign the IO in a PDC file and implement the design to generate the bit stream.

When the design is implemented, we will see this design takes about 28% of the slices and 21% of the Block RAM.

Now we have a bit stream in the next blog we will look at how we create the software and how we can generate the configuration files to run the application from the boot memory.

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