It’s common for many custom FPGA board developments to contain a DDR3 memory. Of course, when we develop a custom board, we need to verify the functionality of the design we are deploying and also the hardware design. This often requires different designs to be loaded into the FPGA at different parts of the verification.
There is always technical risk when developing custom boards and sometimes debugging is needed on more complex interfaces like DDR3. In this blog, we are going to use the Arty A7-35 board as an example and generate the debugging example for the 7 series DDR MIG.
Typically, we use IP integrator when we implement a DDR3 MIG in a 7 series device and we can see the basic status signals which come from that (e.g., completion of initial calibration and tg_compare_error).
Because only the init_calib_complete is present in the user design, there is little additional debugging information which can be used if the behavior of the memory is not as expected.
We can, however, get additional debugging information from the 7 series MIG, although these options are not available when implemented via the IP integrator flow.
The best way to be able to access these settings and debug the 7 Series MIG is to use the example design which is provided when we create the MIG. This example design not only inherits the configuration of the DDR (e.g., device, clocking etc.) but also implements a traffic generator and comparison structures.
Getting started in your development project is simple where you have created your initial MIG settings. Under the sources, right click and select Open IP Example Design.
This will open the example design using your MIG settings.
Since IP integrator is not used within this example design, we are able to configure the MIG to include the debug control signals and define the depth of the ILA.
This example design will be configured for the target device with all the appropriate settings.
Within this example design, you may need to modify the top level for the clocking on the board. In this example, I updated the top level to take in a single 100 MHz system clock from the Arty A7 board and then used clock wizard to generate the system and reference clocks for the MIG. This requires a few simple modifications to the top level RTL.
Once this is completed we are able to build the design and download the bitstream to the target board when it’s available.
Opening the hardware manager will show the ILA which contains several of the debugging signals. We will also see a VIO tab which enables further visibility and control.
Now, of course, we want to be able to effectively work with and understand what these signals mean and the information they provide.
There are several spreadsheets provided with Answer Record 43879 that can be used to aid debugging. This can be combined with UG586 and the debugging section which defines several steps that can be applied to focus in on issues within the design.
The ability to get more information from the MIG is important when working with custom boards which may or may not be exhibiting memory issues.