Over the last five years, I have been writing some very in-depth projects on Hackster in addition to my weekly blogs. These projects have...

After what may seem like ages on many projects, our FPGA designs are ready to be deployed in the field. Of course, by this time, our...

A couple of months ago, I wrote a blog about the lessons I have learned setting up my own engineering business. This original blog...

We’ve looked at the platform management unit (PMU) on the Zynq UltraScale+ MPSoC several times before and especially for inter-process...

We all know that if we want to get the best performance, we should place input clocks to our FPGAs on clock capable or dedicated clock...

This week at TechCrunch Disrupt 2023, AMD announced the next in the series of their very popular Kria SOM platform, the K24. The Kria K24...

Over the years I have talked a lot about how to use FPGAs and SoCs and I’ve even shared tips and advice for how to start your own...

We have created projects and blogs on most AMD families over the years but have never created one for the Artix UltraScale+ (AUP) FPGA....

Over the last few weeks, we have been looking at how we can effectively work with PetaLinux using the ZUBoard as the reference platform....

Last week we looked at how we could use spidev and I2Cdev to work with devices which use SPI or I2C interfaces. These are commonly used...

Regular readers of this blog and my Hackster projects will note that I tend to use either bare metal applications or PYNQ when developing...

We have used Integrated Logic Analysers (ILA) several times in our blogs and Hackster projects to ensure our designs are working as...

One of the great things about programmable logic is its versatility. It is at the heart of a range of systems from handheld embedded...

As we have discussed several times in this blog, programmable logic is ideal for the development of image processing systems due to its...

Over the last few weeks, we have looked at some interesting aspects of the 7 series and UltraScale / UltraScale+ clocking buffers. To...

Last week we looked at how we could use 7 series clocking resources to provide integer clock division without using MMCM. In this week’s...

Many of our FPGA designs are multi-clock, meaning several clocks within the design, which can introduce clock domain crossing challenges....

One common question on forums, twitter and r/FPGA is how to go about setting up on your own as a freelancer or consultant. Often the...

In September 2013, I was about to start a new role, as head of electronics at a space imaging developer when what should arrive in the...

Designing a successful system requires not only the implementation of the algorithms within the programmable logic and processing systems...