MicroZed Chronicles: Alveo Edition: High Bandwidth Memory.

Over a Over a series of blogs we have been exploring the Alveo V80 board, the Alveo Versal Example Design (AVED) its constituent parts along with how to build and install the necessary host drivers.

This examination has been very technical however, in the final blog looking at the Alveo V80 I would like to talk about the potential application use cases for the Alveo V80. At the heart of the Alveo V80 is of course the Versal High Bandwidth Memory (HBM). The High Bandwidth Memory provided by Versal HBM devices provide up to 32GB of memory within a bandwidths of up to 819GB/s using a HBM2e DRAM.

The capabilities and performance provided by the HBM2e memory make the Alvo V80 ideal for a range of memory intensive applications for example

• High Performance Compute – The high bandwidth and large memory capacity enables acceleration of data intensive computations, thanks to the high throughput and parallel processing capabilities of the programmable logic.

• Video and Image Processing – Real time video processing can leverage the HBM to buffer frames of data for analysis. The capabilities provided by the Alveo V80 also enable on board acceleration of the processing algorithms on the image for example astronomy or medical imaging algorithms.

• Financial Computing – High frequency trading requires low latency access to financial information. HBM removes the need for the financial information to be stored off chip in DDR memories which comes with not only lower bandwidths but also crucially increased latency. The direct opposite of what is required by Financial computing

• AI and ML – HBM provides developers with the ability to pre process information and buffer it within the HBM prior to being accessed by the target accelerator.

Working with HBM within the Alveo V80 or indeed any Versal HBM devices is straight forward. Lets take a look at how we can configure a simple simulation such that we can understand how we can instantiate and work with HBM.

As with DDR memory in the Versal architecture the HBM memory is also connected to the network on chip. As such is we want to instantiate a HBM interface we need to instantiate a AXI NoC within an IP Integrator block diagram.

Examining the AXi NoC settings will show how we con configure the NoC for both HBM and DDR interfaces.

To create the simulation, we can run the block automation and configure it as shown in the image below.

This will result in the following system being creating in IP Integrator.

Examine the Setting on the AXI NOC and ensure the settings are as below.

Click on the Connectivity tab and observe the connection between the AXI interface and the HBM.

Set the NoC bandwidths to 12800 MBps.

On the HBM Configuration, change the HBM clock to internal, leave everything else unchanged.

The diagram should look as below.

Click the run connection automation, select all of the options.

This will regenerate the diagram as below.

Run the block automation for a final time to connect in the external connections.

Reconfigure the NOC Clock generator for 400 MHz.

Reconfigure the AXI traffic generator, to be non synthesisable and have a test pattern of writes followed by reads. Set the AXI write bandwidth to 12800 MBps.

On the AXi4 read channel configuration, set the read length to 127, the AXi read bandwidth to 12800 MBps and the read size to 32 bytes.

Validate the design, this will update the NoC configuration.

Open the simulation settings and enable all signals to be logged and set the simulation run time to 150000ns.

Run the behavioural simulation and you will see at the end of the simulation a summary of performance of the NoC and HBM which is impressive.

Now we can add this knowledge to the AVED and start developing our application which leverages both the AVED and HBM.

Workshops and Webinars

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

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• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

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