MicroZed Chronicles: Linear Interpolation
- Jun 24
- 4 min read
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Along our journey exploring algorithms from first principles, we have previously looked at the DFT, FFT, and polynomial approximation. Continuing this exploration, another very useful technique often implemented within FPGA designs is linear interpolation.
Linear interpolation is used to estimate an unknown value between two known data points by assuming a straight-line relationship between them. Common FPGA applications include sensor linearisation, gamma correction curves, waveform generation, and mathematical function approximation.
To calculate the interpolated value, we need two known points, (X0,Y0) and (X1,Y1). The interpolated value YYY for a given input XXX can be calculated using:
Y=Y0+(X1−X0)(X−X0) / (Y1−Y0)
The term:
(X1−X0) / (Y1−Y0)
defines the slope of the line between the two points. We then scale this slope by the distance from X0X_0X0 and add it to the starting value Y0Y_0Y0.
While straightforward mathematically, this formulation introduces a division operation. Although dividers can be implemented within an FPGA, they consume additional logic resources, increase design complexity, and often add significant latency.
Fortunately, we can reformulate the equation by defining a fractional position between the two X values:
frac=(X1−X0) / (X−X0)
This fractional value ranges between 0 and 1:
When frac =0, the output is Y0
When frac =1, the output is Y1
Intermediate values provide proportionally interpolated results
Using this fractional term, the interpolation equation becomes:
Y=Y0+frac×(Y1−Y0)
his form is commonly referred to as a linear interpolation or lerp function.
Of course, we still need to determine the fractional value. If calculated directly, it would require another division.
However, digital logic provides us with an elegant solution.
If we choose the spacing between interpolation points such that:
(X1−X0)=2^N
then the division becomes a simple right-shift operation. This allows us to eliminate the divider entirely.
This approach is particularly useful when implementing interpolated lookup tables. Consider a sensor linearisation table driven by a 16-bit input and a lookup table containing 256 entries.
The input can be partitioned into:
[15:8] LUT Address
[7:0] Fractional Position
The upper eight bits select the lookup table entry, while the lower eight bits define the position between the selected entry and the next one.
This works because each lookup table segment spans 256 input counts. The lower eight bits therefore naturally represent the fractional position within that segment.
As a worked example, consider the input value:
0x45D0Splitting the value gives:
Address = 0x45 = 69
Fraction = 0xD0 = 208The address value of 69 is used to read Y0 from lookup table entry 69. The next table entry, 70, provides Y1
The fractional value is:
208 / 256 = 0.8125
meaning the input lies 81.25% of the way between Y0 and Y1.
Assume:
Y0 = 1000Y1 = 1400The interpolated value becomes:
Y=1000+(1400−1000)×0.8125Y
Y = 1000 + 325
Y=1325From an FPGA implementation perspective, this maps very efficiently onto the available hardware resources:
BRAM / LUTRAM -> Store Y0 and Y1
Subtractor -> Y1 - Y0
DSP Block -> (Y1 - Y0) × frac
Shift -> Divide by 256
Adder -> Add Y0No divider is required, and the design can be easily pipelined to achieve high clock frequencies.
This approach forms the basis of many interpolated lookup tables used in FPGA applications, providing a good balance between accuracy and resource utilisation.
By exploiting the power-of-two nature of digital systems, we can efficiently implement linear interpolation using only simple arithmetic operations and a single multiplier.
As such, linear interpolation remains one of the most useful techniques for implementing sensor linearisation, gamma correction, waveform generation, and mathematical function approximation within FPGA designs.
I have uploaded a simple example implementation of linear interpolation to my GitHub repository for anyone interested in exploring the technique further.
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