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MicroZed Chronicles: Device DNA and the Explorer Board

1 hour ago
4 min read

As we are about to start production of the explorer boards, I have been thinking things which we do not normally always consider as FPGA engineers. That is post assembly functional test, e.g. does the board do we as expect and function as intended.


The explorer board is both pretty simple and at the same time complex. What makes it complex is that we have to program the PMIC first before we are able to see if the RP2040, Artix UltraScale+ FPGA and all the associated peripherals are functioning correctly. What makes it simple is most connections are to the Pmod of SYZYGY interfaces.



Of course one thing we need to be able to do on every board is serialise it so we can ensure it has been tested. This is where some of the FPGAs capabilities come into it, helping us again reduce the Bill of Material.


Every 7 Series, UltraScale and UltraScale+ device contains a device DNA identifier. In UltraScale and UltraScale+ devices this is a is 96 bits held in eFUSEs, read from the fabric through the DNA_PORTE2 primitive. UG570 notes that the two least significant and two most significant bits are fixed values so the ends of the word can be recognised, with DNA[0] always set. Vivado shows the same 96 bits as REGISTER.EFUSE.FUSE_DNA in the device properties, so on this family the JTAG value and the fabric value are the same number, which makes checking our reader very easy.


A note on 7 series devices as they have the similar capabilities and device DNA and are also very popular for solutions. When it comes to 7 series, the DNA identifier is 64 bits, which JTAG reads in full, but the fabric only reads 57 of them through DNA_PORT, bits 63 down to 7. UG470 is also careful to say that while the 57 bit value is unique in most cases, up to 32 devices in the family can share the same value.


To access the DNA_PORT2 and DNA_PORT we use the primitive defined within the unisim library, vcomponents package.


To be able to access this on the explorer board we are going to take the following approach, display the device DNA within the Explorer System Controller application which connects over web serial and displays board information such as power rails, temperatures and SYZYGY Pods connected. It is a natural place for the information and when it comes to doing production test we the production test application will be able to query the system controller RP2040 over USB to get the DNA data store it in the production logs.


The way I am going to do this is to create a simple application for the FPGA, that contains the system monitor IP and a custom device DNA data IP module. Both these will connect to the same IO pins to the System Monitor RP2040 and communicate over I2C. This way a nice and simple solution enables me to access the DNA data and the device parameters.


Now the knowledgeable will know that we cannot share I2C on the same pins internal to the FPGA as the Sysmon presents tristate IO intended to be connected directly to the top level IO ports.


As such we will create our own I2C interfaces one for the Sysmon which reads the Sysmon over the DRP interface. While the second reads the DNA when it is command to over the I2C interface. This allows the system controller to monitor the FPGA SysMon values and request the FPGA ID when requested.


This approach also provides me a simple solution which can be updated include the necessary test interfaces when we run the full production test as I develop it.


To ensure the RTL module provides the same results, we need to first connect over JTAG and readback the 96 bit unique ID.



The RTL is available for inspection on the github, which you can take and use of course in your own designs.


Running this on the explorer system controller web applications and we can see the live Sysmon information and the board identify information.



This will be very useful for production testing, as we can now identify every board, its test history and all performance data and rather nicely it cannot be changed without changing the FPGA.


The Explorer board is currently doing a limited pre order (100) with boards expected to deliver from this batch in Q1. With sales of the first batch expected to hit around Q2 2027, along with the new book and explorer board course.


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