One of the great things about programmable logic is its versatility. It is at the heart of a range of systems from handheld embedded applications to data centre acceleration and everywhere in between.
Many programmable logic use cases deploy devices from the AMD cost optimized portfolio (COP). The COP is something we have looked at recently in depth with the release of a white paper on how to select the most appropriate COP device for your application. Being confident in selecting the most appropriate COP device can help reduce the development complexity and risk.
In case you missed it, the announcement on June 20 was to give notice of an upcoming Spartan UltraScale+ family.
As I understand it, the new family of UltraScale+ devices will be complimentary to the existing Artix™ UltraScale+ range of devices. I am sure there will be several new surprising features introduced to leverage features demanded by the Spartan UltraScale+ target applications. I would expect to see a range of enhancements which support targeted industries such as Industrial, Robotics, Smart City, Computer Vision, Healthcare, Video and Broadcast.
The announcement from AMD did give away a few hints at features likely to be implemented within the family. I am going to make a prediction that Spartan UltraScale+ aligns closely with what we see in the Spartan 6 family. Spartan 6 continues to be incredibly popular, as demonstrated by the recent product lifecycle extension to 2030. I think it is therefore likely that as some Spartan 6 devices provided transceivers, we will also see some Spartan UltraScale+ devices offer transceivers. The Spartan 6 devices also offered a high IO to logic ratio, which provided significant benefits when implementing IO intensive applications, such as protocol conversion and bridging. I think we will see a similar approach in the Spartan UltraScale+ devices.
I would also expect, like the Artix UltraScale+ family, that these IO are offered in a high density and high performance IO formats. A mix of HD and HP IO will provide developers with the widest range of interfacing capabilities.
The AMD blog also mentioned an upgraded of security features. Again, increased security is crucial for edge deployed applications in the target industries.
One possible use case would be as a companion FPGA, as AMD SoCs and adaptive SoCs are great for many applications. There are some applications which require a separate processor - for example, non-Arm® architectures, niche processor capabilities, or large existing code bases, etc. In this case, the Spartan UltraScale+ FPGA can be connected to the processor using a commonly used processor interface, such as SPI, QSPI, I2C or UART. A simple protocol can be deployed over these common links combined with an associated IP core in the FPGA to convert the SPI into AXI Lite / AXI4 connecting to the device internal AXI network.
This allows the processor to connect to anything within the Spartan UltraScale+ FPGA, which is connected to the AXI network. This enables the processor to be able to leverage the Spartan UltraScale+ for interface expansion, bespoke interfacing or processing acceleration / offloading. If you want to know more about how this processor to AXI network can be implemented, I wrote a recent Hackster project which shows the scheme used for a simple AXI Lite interface. Many of our Adiuvo FPGA developments include a similar IP, which also support AXI4 and full burst capabilities to enable high bandwidth accesses, either connected to an external processor or to a UART for debugging and board bring up.
Like all other devices in the 7 series family, UltraScale™, UltraScale+ and Versal adaptive SoCs will use the Vivado™ and Vitis™ software environments. This allows projects to be easily ported from other COP devices and leverage the large IP library in IP Integrator.
While more detailed information on the Spartan UltraScale+ family will be forthcoming, I am looking forward to learning more about this family. I think it is going to slot into a nice gap in the COP, which means I will need to update the white paper soon.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with petalinux OS
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
AMD sponsored this blog, and opinions expressed in this blog are those of Adam Taylor. AMD, the AMD Arrow logo, Artix, Spartan, UltraScale, UltraScale+, Vitis and Vivado and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this blog are for identification purposes only and may be trademarks of their respective companies