MicroZed Chronicles: FPGA Horizons Journal Issue 4

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One of the things I've always enjoyed over the years is sharing my passion for FPGA design, whether that's through blogs, projects, or demonstrations showing how to build FPGA-based solutions.

Since I started, the FPGA Horizons Journal it has become increasingly popular and attracted some excellent articles covering a wide range of FPGA technologies and applications. Issue 4 has just been released, so this week I thought I'd take a look at some of the articles that particularly caught my attention.

How to Render Cloud FPGAs Useless (and Why It Is Surprisingly Hard to Kill One)

The cover story comes from Professor Dirk Koch and the Novel Computing Technologies Group at Heidelberg University. Like many electronic devices, FPGAs are increasingly becoming targets for malicious actors. Until recently, attacking an FPGA generally required physical access, a laboratory, oscilloscopes, and EM probes. Today, with cloud-deployed FPGAs, all that's required is an account and the ability to run your own design on someone else's hardware.

The article explores several attack primitives that can be implemented directly within the FPGA fabric, beginning with the humble ring oscillator. By feeding a LUT output back to its input using the appropriate truth table, it oscillates and becomes a temperature- and voltage-dependent sensor. Cloud providers naturally scan for these structures, but the researchers demonstrate how a transparent latch can disguise the oscillator sufficiently to pass design rule checks while operating at frequencies between 1.6 and 1.8 GHz. Combined with a time-to-digital converter, this enables sub-10 picosecond measurement accuracy—effectively creating a remote oscilloscope capable of side-channel analysis.

What I found particularly interesting was how the research evolved into a study of FPGA robustness. The team attempted to determine whether they could physically damage a datacentre FPGA remotely. Using high fan-out ring oscillators, they generated approximately 100 mW per CLB, creating a 135 W hotspot across just 1.2% of the device and sustaining it continuously for three weeks. Despite this, the average performance degradation was only 1.39%. While a few interconnects exhibited ageing of up to 70%, the devices continued operating correctly, with some of the degradation recovering over time.

The conclusion is reassuring. Although cloud FPGAs certainly introduce new security challenges and require robust scanning and isolation techniques, physically destroying the hardware remotely is significantly more difficult than many might expect. As FPGA engineers, this should give us confidence in the inherent robustness of modern devices.

If this topic interests you, Dirk will also be presenting HotSpot Design and Analysis on DataCentre FPGAs at FPGA Horizons in October.

Memory on Package – Rethinking How We Build FPGA / Adaptive SoC Systems

Memory is becoming one of the biggest challenges in FPGA-based system design. Not only is memory availability affected by increasing demand, but designing high-speed DDR interfaces remains one of the most complex aspects of PCB development. Layout constraints are demanding, while signal integrity and power integrity analysis are both technically challenging and expensive.

For many designs, the external DDR interface ends up dictating the entire architecture. Memory placement influences pin allocation, I/O bank selection, power distribution and even the PCB stack-up. Add in the need for tight length matching, impedance control and extensive SI/PI verification, and it's easy to see how the memory subsystem often drives the design rather than the compute requirements.

This is where Memory on Package (MoP) offers an attractive alternative. The article introduces AMD's Versal Premium Gen 2 2VP3622 MoP device, integrating 32 GB of LPDDR5X directly within the package. With no external DDR interface to route, there is no SI/PI envelope to close, and AMD estimates that board area can be reduced by approximately 60% compared to equivalent external-memory implementations.

This makes compact form factors such as PXI, 3U VPX and PCIe cards much easier to realise.

Security also benefits. With no exposed DDR traces or byte lanes, probing or tampering with memory becomes considerably more difficult—an increasingly important consideration as regulations such as the Cyber Resilience Act become more influential in edge system design.

Memory inside the package is not entirely new—High Bandwidth Memory (HBM) has existed for several years—but MoP targets a very different application space. While HBM delivers enormous bandwidth for AI and HPC workloads, it comes with tighter environmental constraints and different lifetime considerations. MoP instead provides a factory-calibrated memory subsystem designed for industrial temperatures and long operational life, making it well suited to networking, aerospace, defence and test equipment.

Having personally spent many hours debugging DDR interfaces during board bring-up, and seen clients require multiple board revisions to resolve memory issues, I can certainly appreciate the appeal of starting with a memory subsystem that simply works.

Single Event Testing of the Versal AI Edge Gen 2 Processing System

Regular readers will know that radiation effects are a topic close to my heart.

This article is the third in a series by Dr Pierre Maillard and Dr Abhijitt Dhavlle from AMD covering the radiation resilience of the Versal AI Edge family.

This instalment focuses on the processing system within the 6 nm Versal AI Edge Gen 2 devices. The processing subsystem is substantial, providing eighteen Arm processors in total: eight Cortex-A78AE application processors delivering up to 200k DMIPS alongside ten Cortex-R52 real-time processors, with both full-power and low-power domains and lockstep capability for safety-critical applications.

Testing a processing system against radiation-induced faults presents very different challenges from configuration memory testing. Errors may occur within cache coherency logic, interrupt controllers or DMA engines, and there is no universal benchmark that adequately exercises every subsystem. AMD addresses this using its System Validation Tool (SVT), generating constrained-random traffic across the entire processing system while verifying the observed behaviour against expected results.

Testing used both 64 MeV proton beams at Crocker Nuclear Laboratory and broad-spectrum neutron testing at Los Alamos, completing over one million SVT iterations with an accumulated radiation exposure equivalent to more than 1.5 million years of natural sea-level radiation.

The results are impressive. No single-event latch-up was observed, even under worst-case operating conditions of maximum voltage and 110°C. ECC mechanisms successfully corrected every cache and RAM error encountered, with no uncorrectable failures recorded. The overall processing system SEFI rate was approximately 2 FIT, while error coverage exceeded 99% in accordance with ISO 26262.

One particularly valuable takeaway is that, while vendor FIT data provides an excellent starting point, testing your own application and configuration remains the best way to understand the behaviour of your complete system.

Selecting a Scalable FPGA Platform – Migrating from a Legacy FPGA

Rachael Peterson, Design Authority and Principal Engineer at Concurrent Technologies, discusses a challenge many FPGA engineers will recognise.

For many years, Concurrent's embedded computing products relied on a mature flash-based FPGA to manage power sequencing, reset control and board support functions. It proved to be a reliable solution for almost two decades, offering instant-on capability and low power consumption.

However, modern Intel processor architectures increasingly integrate these responsibilities into the SoC itself, while reducing I/O voltages from 1.8 V to 1.0 V and 1.1 V. Combined with I/O limitations on the existing FPGA, continuing with the previous architecture was no longer practical.

What I particularly liked about this article was the structured evaluation process. Rather than simply selecting a replacement that met today's requirements, the team considered long-term scalability, ecosystem maturity and future product evolution. AMD ultimately offered the strongest roadmap.

The migration begins using an Artix-7 on an Arty A7 development board before moving to Spartan UltraScale+, allowing configuration, clocking and DDR interfaces to be validated early while reducing overall project risk.

The article also highlights how integrated debugging using ILA and VIO cores allowed rapid diagnosis of eSPI and power sequencing issues directly on hardware, avoiding lengthy simulation cycles. Rather than remaining a simple support device, the board-support FPGA evolves into a capable processing platform using MicroBlaze V and standard AXI infrastructure to complement the host processor.

Post-Layout Signal Integrity

The final article comes from Dan Binnun of E3 Designers and builds upon his pre-layout signal integrity article published in Issue 2.

Dan is someone I've worked closely with—we co-authored a hardware design book together—and he was instrumental in the success of the Explorer board by performing the SI and PI analysis. Having seen the value of this approach first-hand, I found this article particularly enjoyable.

Post-layout SI represents our final opportunity to validate a PCB before committing it to manufacture. The staged methodology described begins with automated impedance and crosstalk analysis using tools such as Ansys SIwave before progressing to detailed S-parameter extraction and channel simulation.

These automated checks provide a valuable fresh set of eyes, quickly identifying incorrect trace widths, poorly matched differential pairs or routing across split reference planes—issues that are surprisingly easy to overlook after spending weeks refining a layout.

Extracted S-parameters can then be compared directly against interface specifications, such as PCIe return-loss requirements, or used within full channel simulations to assess eye diagrams, bit-error rates and overall design margin before release.

As FPGA designs increasingly incorporate multi-gigabit interfaces and high pin-count devices, this approach transforms post-layout SI from a final sanity check into a genuine verification activity. The goal, as Dan says, is not to discover whether the design works, but to confirm that it does.

Wrapping Up

Issue 4 demonstrates once again why FPGA Horizons has become such a valuable resource for FPGA engineers. The articles cover an excellent mix of emerging research and practical engineering, from cloud security and radiation resilience through to memory architecture, migration strategies and board-level verification.

These five articles alone make the issue well worth downloading, and there is plenty more besides, including UVVM verification and several other excellent contributions. If you're involved in FPGA development, whether you're interested in cutting-edge research or solving real engineering problems, I would strongly recommend downloading Issue 4, along with the back catalogue, from fpgahorizons.com. It is well worth your time.

FPGA Conference

FPGA Horizons London- October 6th and 7th 2026 - get Tickets here.

FPGA Journal

Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.

Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

• Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

• Professional PYNQ Learn how to use PYNQ in your developments

• Introduction to Vivado learn how to use AMD Vivado

• Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

• Arty Z7-20 Class looking at HW, SW and PetaLinux

• Mastering MicroBlaze  learn how to create MicroBlaze solutions

• HLS Hero Workshop  learn how to create High Level Synthesis based solutions

• Perfecting Petalinux  learn how to create and work with PetaLinux OS

Boards

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• Adiuvo Embedded System Development board - Embedded System Development Board

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• SpaceWire RMAP Initiator - SpaceWire RMAP Initiator,  digital download, AXIS & AXI4 Interfaces

• SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

• Other Adiuvo Boards & Projects.

Embedded System Book   

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All words in this blog were written by a human.