MicroZed Chronicles: DisplayPort

One of the recurring themes across many of my blogs and projects is the development of image processing solutions. Typically, these solutions are output to a display—most often HDMI, and occasionally DisplayPort.

DisplayPort is particularly useful for MPSoC-based image processing applications because it is integrated within the Processing System (PS) of the device and outputs via the PS GTR transceivers. Using the PS DisplayPort, we can generate graphics from DDR memory, output live video streams, or combine live video with graphical overlays.

DisplayPort Overview

If you are not familiar with DisplayPort, it differs from HDMI and VGA in that it is a packet-based protocol. This allows it to transmit video, audio, and auxiliary data over high-speed differential links.

For DisplayPort 1.2a, these links operate at data rates of 1.62, 2.7, or 5.4 Gbps, depending on the negotiated link configuration.

DisplayPort uses two independent communication channels:

• Main Link – A unidirectional, high-speed multi-gigabit link used to carry video and audio data.

• Auxiliary (AUX) Channel – A bidirectional channel operating at 1 Mbps, used for sideband communication such as link configuration and status monitoring.

Link Training

Establishing a DisplayPort link involves two stages of link training:

1. Clock Recovery - The source transmits a training pattern while adjusting the voltage swing. The sink locks onto the clock and confirms successful recovery.

2. Channel Equalisation (Symbol Lock and Lane Alignment) - The sink aligns symbols and lanes (if multiple lanes are used) and confirms correct data reception.

   
   

Feedback from the sink during both stages is communicated via the AUX channel.

Once link training is successful, active video transmission can begin.

Video Transmission

DisplayPort transmits video using fixed-size Transmission Units (TUs), which are distributed across the active lanes using 8b/10b encoding.

To allow the sink to reconstruct the pixel stream, Main Stream Attributes (MSA) are transmitted. These include:

• Resolution

• Timing information

• Colour depth

• Pixel clock information

MPSoC DisplayPort Pipeline

The MPSoC PS includes a highly capable DisplayPort video pipeline, which is largely configured through software (e.g. using Vitis).

The pipeline supports:

• Live video input from the PL

• Graphics from memory (DDR)

• Test pattern generation

  
  

These inputs can be combined using:

• Alpha blending

• Colour space conversion (CSC)

A particularly useful feature is that the blended video output can also be routed back into the Programmable Logic (PL) for further processing.

DisplayPort API Implementation

To simplify the use of DisplayPort in my designs, I created a small API to configure the PS DisplayPort for live video output.

Initialisation

The API begins by configuring the key components:

• XDpPsu_InitializeTx - Initializes the DisplayPort TX subsystem, including AUX clock, HPD detection, and PHY configuration.

• XAVBuf_InputVideoSelect - Selects the live video stream from the PL (XAVBUF_VIDSTREAM1_LIVE).

• XAVBuf_SetInputLiveVideoFormat - Configures the input format (e.g. RGB 12 bits per component, matching the 36-bit PS interface).

• XAVBuf_SetOutputVideoFormat - Sets the output format (e.g. RGB 8 bits per component for monitor compatibility).

• XAVBuf_ConfigureVideoPipeline and XAVBuf_ConfigureOutputVideo - Configure the blending pipeline and CSC coefficients.

• XAVBuf_SetAudioVideoClkSrc - Selects the video clock source (typically from the PL).

• XAVBuf_SoftReset - Resets and synchronises the pipeline with the configured clock domain.

  
  

Link Management

Once initialised, link management is handled via interrupts, on a Hot Plug Detect (HPD) event:

• XDpPsu_GetRxCapabilities - Reads the sink’s capabilities (lane count, link rate, framing support).

• XDpPsu_SetLaneCount - Configures the number of lanes supported by the board.

• XDpPsu_SetLinkRate - Sets the link rate to the maximum supported by the sink.

The DisplayPort subsystem then performs:

• Clock Recovery

• Channel Equalisation

  
  

Video Configuration

After successful link training:

• XDpPsu_CfgMsaSetBpc - Configures bits per colour.

• XDpPsu_CfgMsaUseStandardVideoMode - Sets the desired video mode and timing.

• XAVBuf_SetPixelClock - Programs the VPLL to generate the required pixel clock.

At this point, the DisplayPort output should be fully operational.

Results

I tested this implementation on the ZCU106 using a live MIPI camera input, and the output was successfully displayed via DisplayPort.

Conclusion

The PS DisplayPort within the MPSoC provides a powerful and flexible solution for video output in image processing applications. With support for live video, graphics blending, and a fully configurable pipeline, it enables rapid development of sophisticated display systems.

As always, the full source code for this implementation is available on my GitHub.

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