A few weeks ago, we looked at what to do if you experience issues with DDR3 when bringing up a new board. In this blog, we are going to look at what we can do to debug DDR4 issues when bringing up a board.
To do this, we need a board that provides DDR4 connected to an UltraScale or UltraScale+ device. We will be using a ZCU102 which has 512 MB of DDR4 connected to the PL side of the Zynq UltraScale+ MPSoC ZU9EG.
Of course, significant design and analysis work needs to be done during both the schematic design and layout phases when developing custom hardware which uses DDR4 or LPDDR4. This ensures that signal and power integrity are such that the implementation will be successful. If you are considering designing your own FPGA-based board that uses DDR4, I recommend you read User Guide 583 (UG583) as a starting point. Within this guide, you’ll find an overview of the DDR4 signals and also information including fly-by and clamshell topologies, along with techniques to ease routing in clamshell-like address mirroring. UG583 also provides a range of very useful ECC connection rules and routing guidelines. Before you consider designing in DDR4 to your application, read this user guide and download the DDR4 checklist!
We need to be able to bring up the DDR4 memory on the board once it comes back, however, this should not be the first time you create a project targeting the DDR4.
To get started, we should create a design in Vivado which implements the DDR4 MIG configured for the DDR4 device.
As part of this project, I also enabled the debug signals for the DDR4 MIG which are available in IP Integrator and very useful during bring up.
To ensure the pin allocation is valid, we should be generating this project early while the board is still in development and well before layout is signed off. One difference between the DDR3 MIG is that the pin allocation takes place within Vivado’s IO planning.
My completed project for the DDR4 MIG on the ZCU102 can be seen below. Note how I connected the DDR4 debugging signals to a ILA.
Once the project has been built, we can download the bitstream to the device using the hardware manager. We will also see a tab opened within the hardware manager which provides significant information on the DDR4 implementation. This will include information on the core configuration, calibration information, and the windows.
If you experience issues with the DDR4 on your board, there are several things which can be performed to identify the root cause. The checklist previously downloaded also has a helpful tab which can guide the stages of debugging.
The debugging section in Product Guide 150 (PG150) will be critical and provides a wealth of information on debugging the design.
Naturally the first things to check are the basics including clocks (present and locking), resets (correct polarity), and licensing.
The next step is to examine the hardware level and if all unused pins are driven correctly, voltages and terminations are correct etc. Again PG150 has an exhaustive list of parameters to check at the hardware level.
If the issues appear to be during calibration, it is crucial to determine where in the calibration phase it is failing and the exact bit which is causing the failure. The failing calibration stage is reported in the ILA status window.
It’s in the debug signals that we broke out earlier which can be very beneficial in determining the cause of the issue in addition to reading data from the DDR4 XSDB instance using TCL scripts.
The steps to be followed at this stage depend on the point at which the calibration is failing. PG150 has detailed debugging steps for each element and following these should hopefully get you going or help you identify the root cause of the issue in addition to the corrective mechanism needed.
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Embedded System Book
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We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here
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