A few weeks ago we looked at the GateMate FPGA from Cologne Chip. In this blog we are going to explore the GateMate FPGA tool chain and how we can get an initial hello world application up and going.
The tool chain uses opensource tools such as Yosys and OpenFPGALoader, in co-operation with a Cologne Chip developed implementation and bitstream generation tools. When it comes to design entry engineers can use Verilog, VHDL (Via the Yosys HDL add-in) along with support for AmaranthHDL, SpinalHDL and Silice.
To obtain the tools we need to create a myGateMate account, once access is granted we are able to download the software which supports both Windows and Linux operating systems. Compared to many FPGA tool chains the download is light, at around 25 MB.
Within the download compressed file you will find a binary area which contains all of the binaries and a workspace which contains several example projects. These projects include the classic blinky and a multiplier example.
Along with the examples and binary is a very useful getting started guide.
As you may have assumed this tool chain uses command line to control the synthesis, implementation and programming.
Examining one of the reference projects will provide a good example of how we need to create a project. Helpfully the examples are provided in both Verilog and VHDL format which enables both flows to be demonstrated.
At the top level of this workspace, you will see a file called config.mk this file contains the locations of the executables within the binary folder. Along with defining the tool chain targets, JTAG, source and simulation targets. Using this config file we are then able to use it as a reference for make files within our workspace, this makes it easy to create and work with new projects.
If you are using a windows based system you will find a run.bat file within each of the project directories which provides a similar function to the make files on Linux systems.
Each project has a simple structure with several directories which are used to store elements of the project from log to netlist, simulation results and source files.
Within the SRC directory you will find the example Verilog and VHDL files for the demo along with a CCF file. The CCF file is the constraint used within the GateMate FPGA flow, the example files provided outline all of the necessary commands for IO placement and valid options.
One of the nice things about the command line flow is we can easily integrate it within VSCode.
To build the VHDL example we can use the command run.bat synth_vhdl very quickly we will see the results of the synthesis appearing in the log folder and the resulting Verilog netlist being under the net folder. Opening the log folder will show the results of the synthesis.
To create the implementation we can run the command run.bat impl once this command is run you will see several new files being created at the top level of the project directory. These files will include the bitstream, reports and other information on the implementation of the design.
The implementation process also provides developers with a Verilog netlist and associated SDF to enable post implementation simulation.
With the implementation completed we are able to program the GateMate FPGA development board also using the OpenFPGALoader.
This should result in the FPGA flashing on the board, along with the programmed LEDs showing successful loading. We can also use this loader to flash the non volatile SPI device on the board to become the default program when booting from the SPI.
I like this board and its tool chain, it feels very nice and simple to use and work with.
I still have a couple of things to investigate like timing of the design etc. However, I can see several applications which could be of use for this device especially things like system monitoring and control.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with petalinux OS
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.