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Delving into Renesas ForgeFPGAs: A Primer on Low-Density Logic Solutions

One of the FPGAs I have wanted to examine since it was announced is the new Renesas ForgeFPGA. These devices offer developers a low-density logic solution that can be used for applications where low-density logic is beneficial, such as interfacing, system control, sequencing, and system monitoring. The ForgeFPGA is complementary to the very popular GreenPAK range, which provides configurable programmable mixed-signal solutions.

ForgeFPGA in comparison to a penny

ForgeFPGA Development Kit with FPGA socket.

As low-density FPGAs, each ForgeFPGA offers developers:

  • 1120 5-bit Look Up Tables.

  • 1120 Registers.

  • 5 kb of distributed memory.

  • 32 kb of BRAM.

  • 50 MHz onboard oscillator.

  • Phase-locked loop.

The CLB structure of the ForgeFPGA provides developers with 8 flip-flops per CLB. The logic element of the CLB is provided by four 6-bit Look Up Tables, which are implemented by pairing two 5-bit LUTs. Each of the 6-bit LUTs has two outputs, each with an associated D-Type flip-flop.

Using a 6-bit LUT provides developers with the ability to implement more logic functions within a single LUT. This has the advantage of enabling better performance for larger logic equations, while the ability to split into two 5-bit LUTs ensures the best utilization of resources for logic equations with fewer terms.

Within the SLG7910 device, there are 140 CLBs, with 100 being CLBs for logic and the remainder for memory. The main difference between the two is that the CLBM also provides extended modes such as Embedded Memory Mode (EMM) or Shift Register Mode (SRM).

In EMM mode, each module can be configured to provide four separate 32x1 bit memory blocks, dual 64x1 bit memory blocks, or a single 128x1 bit memory block. The CLBM together forms the 5Kb of distributed memory.

While in SRM, just like in EMM, we can have four 16-bit shift registers, two 32-bit shift registers, or one 64-bit shift register.

The internal organization of the FPGA is shown below, with the BRAMs connected to the FPGA core, along with the internal oscillator and, of course, IO.

To develop the FPGA bitstream, we need to use the Renesas Go Configure software, which enables us to both capture the design and generate the bitstream. To capture the design, we can use Verilog or a schematic entry approach.

If you are a VHDL user, all is not lost, as you can leverage Yosys to convert your VHDL design into a Verilog netlist for implementation. Go Configure is license-free and provides support for a range of devices in the GreenPAK range, not just the Forge FPGA.

When it comes to configuration, the device can be configured either from internal one-time programmable memory or via SPI. When SPI is used, the Forge FPGA can be either the master, in which case it loads the application from an external SPI device, or the slave, where the FPGA receives the bitstream from an external device such as a microcontroller or processor.

To get started with developing for the Forge FPGA, there is a Forge FPGA evaluation board that provides developers with the ability to insert the Forge FPGA within a carrier, along with providing Pmod and GPIO interfaces. Using this board, we can program the device's OTP memory or emulate the design with the program downloaded over SPI. This allows us to prototype and validate our application before programming the OTP.

In our next blog, now that we have examined the Forge FPGA, we will begin to look more at the Forge FPGA evaluation board and the development flow to create an application.


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