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Delving into Renesas ForgeFPGAs: Tool Chain and Dev Board Walk Through

In our previous blog we introduced the Renesas ForgeFPGA, in this blog we are going to walk though the creation of a simple project using the Go Configure software.

To get started we first need to download and install the Go Configure software, with the software installed we are able to open Go Configure and start creating our application.

Once the software is opened we will observe the capability to target not only the ForgeFPGA but also the GreenPak device range using the same software.

In this instance I am going to select the SLG47910V Rev BB FPGA device and in the bottom corner create a new project.

The creation of a new project will open a new dialog box which allows us to set the operating conditions, project information and security settings for the OTP RAM. At this stage I provided the correct operating voltages and temperatures, I wished my ForgeFPGA to operate across.

Having define the project settings the next step is to start creating the application. The dialog presented shows the FPGA, its IO and resources.

To start working on the FPGA development we need to select the FPGA editor option from the top menu bar.

This will open the FPGA development environment, it is in this environment that we are able to create applications, synthesise, allocate IO and generate the bit stream.

To get started I am going to use a simple file which toggles a LED at 0.5 Hz, the code can be seen below

(* top*) module clock_divider( clk, led, osc_en);
	 (* iopad_external_pin, clkbuf_inhibit *) input clk;
	 (* iopad_external_pin *) output led;
	 (* iopad_external_pin *) output osc_en;
    // 50,000,000 clock cycles for 1 second at 50 MHz
    localparam integer COUNTER_MAX = 50_000_000 / 2;  // Divide by 2 for toggling
    reg [25:0] counter; // 26-bit counter to count up to COUNTER_MAX

    always @(posedge clk) begin
            if (counter == COUNTER_MAX - 1) begin
                counter <= 26'b0;
                led <= ~led; // Toggle LED
            end else begin
                counter <= counter + 1;
	assign osc_en = 1'b1;

The ForgeFPGA tool supports Verilog 2005 and System Verilog syntaxes. It also as you can see from the code above uses some specific attributes.

  • (* top*) is used to define the top level of the design

  • (* iopad_external_pin*) is used to define the external IO

  • (* clkbuf_inhibit *) is used to prevent insertion of clock buffer insertion by the synthesis tool. The clock at the top level requires this attribute to be added.

To help us develop our application there is a a IP library provided which contains a range of very useful IP. This spans communication, to peripheral and signal processing, these can be very useful for the applications which the ForgeFPGA is targetted for.

With our simple application built the next step is to synthesise and assign the pins. For this application I will be using the internal 50HMz oscillator.

Assigning the IO is straight forward we can use the IO Planner to assign the pins.

For this project I am targeting the Renesas ForgeFPGA Evaluation board. This board provides a socket for the ForgeFPGA allowing is to program and test the OTP elements of the design and still replace the FPGA easily. Along with the FPGA socket the board breaks out most of the IO and provides two Pmod interfaces. Programming is provided via a USB C interface, with status LEDs provided.

I assigned the clk signal to the OSC_CLK input, the LED signal to GPIO0 OP and ensured the oscillator was enabled by using the OSC_EN signal which is set to a constant high.

With this completed the next step is to implement the design, click the generate bit stream and the place and route algorithm along with the bitstream generation will run.

With a bit stream available we can close the FPGA editor and back in the ForgeFPGA workshop we are able to the ForgeFPGA Evaluation Board.

With the ForgeFPGA evaluation board connected to the development machine over USB, we can then use the debugging controls to start testing on hardware.

Selecting emulation will program the ForgeFPGA over the SPI but not its OTP allowing multiple revisions to be downloaded tested. When we are ready to program the OTP we can select the program option.

Connecting a Digilent Discovery 3 we can see the OP toggling as we intended, not the most exciting output but one which would drive an LED if attached to the connector.

The ForgeFPGA is ideal for many applications which need a small level of digital logic, I will take a look a little at a more complicated example / project soon.



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