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Lattice Launches FPGA for Space!

As readers of this blog will know, my company does a lot of design and development in the space industry. This includes developing FPGA solutions to designing boards and writing software.


We literally do it all so I was very interested to see a recent press release from CAES and Lattice announcing the Certus-NX-RT and CertusPro-NX-RT FPGAs. These devices are up screened and qualified version of the Certus-NX and CertusPro-NX FPGAs.

In this blog, we’ll take a look at these devices and the information that is publicly available. I think these devices will be very interesting additions to the market, especially to the control plane developments where communications, system supervision, management, telemetry, and implementation of control algorithms are critical.


Starting from the beginning, the first available part is the UT24C07 which is a Certus-NX-RT and offers 39K logic units, 56 DSP elements, 2.5 Mb of memory and 100K rad and <80 MeV for SEL.



In addition to the logic and memory resources, the device also offers the following features:

  • Support for DDR2/3L or LPDDR2/3

  • Two 1 MSPS 12-bit ADC providing a total of 16 differential inputs

  • Cryptographic engine supporting AES256, ECDAS, SHA, HMAC and true a random number generator

  • Hard marco implementations of PCIe and CDR for SGMII

  • 192 User IO

All of this is provided in a 256 ball grid array plastic package with an operating temperature between -40C and 125C.


Perhaps the most important feature of the new devices is the fabrication technology which is implemented using a 28 nm fully depleted silicon on insulator (FD-SOI). In addition to reducing the power, this technology also reduces the SI transistor channel, thereby reducing the potential charge area for Single Event Effects. This means the user experiences a lower SEE rate and the SRAM configuration rate is also much lower.


Why do these devices interest me?

Beside the Single Event Effect performance, the most important reason is their ability to hit power and thermal budgets. FD-SOI offers both increased SEE performance and also significantly reduced power. This is important for the development of space hardware because power budgets are always constrained, especially as we must design for the end-of-life worst case scenario. This end-of-life worst case can be considerably larger than start of life after the Total Ionising Dose has been accumulated.


One of the key aspects of any space electronic design is being able to achieve the performance required while still maintaining an acceptable thermal solution. This means two things. The first is that the overall electronic system must be within the thermal interfacing requirements for its mating satellite panel. The second is that designers must achieve challenging derating requirements which are designed to reduce the electrical and thermal stresses on components to achieve reliability. Derating requirements for junction temperature on active devices like FPGAs can be challenging, especially at the end of life when the power dissipation is high.


The FD-SOI implementation of the new Lattice / CAES Certus-NX-RT and CertusPro-NX-RT FPGAs means the power required by the FPGA, even at end of life, is low. This reduction in power helps engineers achieve the power budget for the mission, and since the power dissipation is reduced, it also means the junction temperature is reduced allowing the required derating to be achieved. This also leads to a reduced and simplified thermal solution and anyone who designs for space knows how significant that is.


Outside of the Single Event Effects, power, and thermal solutions, I am also keen to see what the CAES Gaisler business unit located in Sweden can bring. Working closely with the European Space Agency, Gaisler has a strong history in FPGAs, ASICs, and IP development for space. Offerings from Gaisler includes IP cores and solutions like the Leon4 Fault Tolerant and NOELV a RISCV which includes fault tolerant features. Coupled with a long list of other commonly used IP cores, these offers a good range of high quality flight-ready IP which can accelerate development.

Libraries and design tools for Lattice / CAES devices - source CAES


As a company, I think Adiuvo is going to be exploring these devices and their capabilities further as we help our clients address their flight challenges.


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