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MicroZed Chronicles: Lab Equipment
I have written several blogs about setting up and running your own company ( P2 here ) , the software tools and IT infrastructure ...
Dec 4, 20245 min read


MicroZed Chronicles: ChipScoPy
When it comes to debugging designs the more visibility and control we have over debugging elements such as ILAs is critical. When we...
Nov 27, 20244 min read


Altera Agilex 5E Premium Development Kit and NIOS V
In our last instalment we configured the tool chain and started the creation of the example design for the Agilex 5E Premium development...
Nov 21, 20243 min read


MicroZed Chronicles: DSP58 and FP32 Mode
Last week we examined how we could use the IEEE VHDL 2008 fixed and floating packages to implement a simple polynomial approximation. ...
Nov 20, 20244 min read


Altera Agilex 5 Setting up the tool chain
Over this series of blogs we have explored the Altera Agilex 5 devices and their architecture. Of course nothing beats getting hands on...
Nov 18, 20243 min read


MicroZed Chronicles: Fixed and Floating Point Maths
A short time ago I hosted a webinar which looked at how we can implement mathematics within programmable logic. In this webinar we...
Nov 13, 20245 min read


MicroZed Chronicles: Organising Test Benches.
When developing FPGAs there is a critical triad which needs to be achieved for the successful delivery of a project. First we need to...
Nov 6, 20248 min read


Cologne Chip: SpaceWire
One of the many uses of FPGAs is in implementing bespoke communication protocols. At Adiuvo we do a lot of work in the space and high...
Nov 5, 20244 min read


MicroZed Chronicles: Synchronous CDC
Every digital / FPGA designer should be aware of clock domain crossing between asynchronous clock domains. As our devices get more and...
Oct 30, 20244 min read


MicroZed Chronicles: Baseline Timing Closure.
One of the main challenges FPGA designers face, especially those new to FPGA design is how to achieve timing closure. While it seems...
Oct 23, 20244 min read


MicroZed Chronicles: Accelerating FPGA Design Cycles with IP Cores and Open Libraries
The goal of professional FPGA development is to deliver projects on quality, on time, and within budget. Achieving this, however, can be...
Oct 16, 20243 min read


MicroZed Chronicles: From Bits to Plots: Visualizing XADC Data with Python
One of the things I enjoy is when people reach out with suggestions for blogs and projects that would help them. A recent suggestion was...
Oct 9, 20244 min read


MicroZed Chronicles: Python Scripting Solutions with Vitis
To make my blogs and demonstrations illustrative I often use captures from the graphical user interface. However, professionally as an...
Oct 2, 20244 min read


MicroZed Chronicles: Spartan 7 Tile and System Controller.
Over the last few months we have been developing a tile, which contains a Spartan 7 XC7S25 and all of the supporting peripherals...
Sep 25, 20245 min read


MicroZed Chronicles: Interviews
Recently, I've seen a lot of questions about how to prepare for interviews, especially for those looking to land their first FPGA job or...
Sep 18, 20245 min read


MicroZed Chronicles: Petalinux and the AXI Lite UART
The peripherals we communicate with in embedded systems use a wide range of interfaces from I2C, UART, SPI to Gigabit ethernet and PCIe....
Sep 11, 20243 min read


MicroZed Chronicles: Turning Concepts into Reality, The FPGA Screen Challenge
A few weeks ago, I outlined several beginner-friendly FPGA projects to help you get started with your chosen development language....
Sep 4, 20244 min read


MicroZed Chronicles: Perfecting Pipelining
One of the main methods of increasing timing performance in our FPGA designs is to implement pipelining. At its heart, pipelining allows...
Aug 28, 20243 min read


MicroZed Chronicles: Beyond Basics—Intermediate FPGA Projects
I am often asked in emails and social media such as LinkedIn / (X) Twitter, what projects people learning FPGA should look at that are...
Aug 21, 20244 min read


MicroZed Chronicles: RISC-V based Image Processing
FPGA are excellent for image processing, their parallel nature easily allows us to implement parallel processing stages. Over the years...
Aug 14, 20245 min read
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