AMD

Readers of the blog will know I am a huge advocate of System on Modules (SoM) like the K26, MicroZed, PicoZed, UltraZed and of course the...

A couple of weeks ago we looked at the Trenz TE0950 development board which contains a Versal AI Edge XCVE2302 device in ES1. This means...

When we develop an Alveo solution using the Vivado flow, unlike with Vitis flow we do not get a dynamic and static element. Instead we...

One of the questions people often ask me is how to get started on the journey of learning about FPGAs. Of course, everyone’s journey is...

In the 2024 MicroZed Chronicles, we are going to examine Versal in depth with a particular focus on the AI Edge series. We’ve looked at...

Over the last few months, I have written several blogs which examine the key aspects of setting up and running your own...

In our last blog we discussed an E Ink / ePaper driver that I had designed. Today we are going to discuss how to integrate it with a Zynq...

One of the biggest challenges you might face if you want to start working with Alveo either on premises or in the cloud is to identify...

The great thing about FPGAs is that they allow us to create very efficient interfaces for a range of applications. I recently came across...

Developing FPGA solutions can be a challenge and as a consultant, I often see designs which are facing difficulties late in the...

I remember being sat in the crowd at Xilinx Developer Forum 2018 (XDF18) when Xilinx CEO, Victor Peng announced upcoming Alveo PCIe based...

Learning how to develop FPGAs and embedded systems can be a challenge so I like to think that this blog has provided significant support...

We’ve looked at using PetaLinux on our SoCs and MicroBlaze several times throughout our journey. Embedded Linux, however, does not always...

We will be releasing a new open source development board in a few weeks and will eventually be offering a free training course for it,...

If you’ve been working with Vitis 2023.1, you’ll already be aware that a new Vitis Unified Integrated Design Environment (IDE) was...

Over the last five years, I have been writing some very in-depth projects on Hackster in addition to my weekly blogs. These projects have...

After what may seem like ages on many projects, our FPGA designs are ready to be deployed in the field. Of course, by this time, our...

A couple of months ago, I wrote a blog about the lessons I have learned setting up my own engineering business. This original blog...

We’ve looked at the platform management unit (PMU) on the Zynq UltraScale+ MPSoC several times before and especially for inter-process...

We all know that if we want to get the best performance, we should place input clocks to our FPGAs on clock capable or dedicated clock...