A couple of weeks ago we looked at the Trenz TE0950 development board which contains a Versal AI Edge XCVE2302 device in ES1. This means the device is engineering silicon, however, the production version will contain production silicon.
In this blog, we’re going to create a simple Versal design which will cover many of the basics needed to get started creating solutions. I find simple blogs that explain the basics tend to be the most helpful and allow us to build upon them at a later stage.
This solution will use more than just the processor cores to say hello world, however. I’m going to demonstrate how to create a simple design in the PL that connects to the network-on-chip (NoC) which is accessible from the processor system.
We will also come back to some of the concepts explained here and perform a more detailed deep dive in later blogs.
To get started, we are going to create a project which targets the Trenz TE0950 development board.
Once the project is created, we are going to create a new block diagram and add the control, interface and processing system (CIPS). The CIPS block is the element which contains the processing systems, configures the MIO interfacing and defines the interfacing within the device. This includes the network-on-chip, XRAM, and AXI interfaces etc.
Something to note that is slightly different than earlier devices is that the DDR controller is not contained within the CIPS IP block, but instead contained within the network-on-chip.
With the CIPS added to the block design, the next step is to run the block automation and configure the CIPS for the TE0950 configuration. This will also add and connect the NoC, enabling the DDR controller to be configured.
The resultant block diagram will look as follows.
We can now start to add in the AXI BRAM controller in the PL which will be connected to the NoC. To do this, we first need to add in a AXI BRAM controller to the block diagram. Once this is added, we can also re-customize the NoC to provide an AXI output connected to the PL. This AXI output is what will be connected to the AXI BRAM controller.
Within the NoC, we also need to make a connection from the CIPS Slave AXI interfaces to the Master AXI interface. This enables us to define the connectivity of the NoC. In the example below, you can see that all Slave interfaces are connected to the memory controller ports and are enabling DDR access. Note that a PS coherent and PS RPU are also connected to the Master AXI port.
Once we have customized the NoC, we’re also going to re-customize the CIPS block in order to enable a PL clock from the PMC domain and provide a PL reset.
We can then run the connection automation to connect the AXI BRAM controller to the NoC. We can use the PL clock and reset for the clocks and reset as needed within the PL. I also added a constant block to enable the BRAM registers.
We also need to ensure the AXI BRAM controller is within the memory map for the NoC connections from the CIPS.
Next we need to validate the design at which point we will also see a diagram of the NoC and its connection.
With this complete, we can build the bitstream and export the XSA to be used in Vitis. The Vitis flow is identical to how we work with other processors in the AMD line, from the MicroBlaze to Cortex-A9 and Cortex-A53. We simply create a platform targeting our desired processor and create our application. Since this is a straight forward application and demonstration for this blog, I simply adapted the hello world application to write a pattern to the BRAM and viewed the BRAM memory in the debugger view to see the words appear as I stepped through the program.
This shows that the Cortex-A72 within the CIPS system is able to connect using the NoC to read the BRAM located in the PL.
The video below shows a step-by-step walk through of the project.
In a future blog, we are going to delve deeper into many of the concepts introduced here.
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with petalinux OS
Embedded System Book
Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.
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