When we develop an Alveo solution using the Vivado flow, unlike with Vitis flow we do not get a dynamic and static element. Instead we need to create the design from scratch, of course this means we need to be able to implement the PCIe/DMA architecture and the card management and safety functions. Only once we have created this base are we able to then create our application in the remaining programmable logic.
Rather than having to start completely from scratch there is of course an approach we can take which will provide us a solid foundation. This foundation ensures we have correctly configured the PCIe/DMA for the target Alveo and it also creates the necessary card management system to provide all of the health and safety management of the device including in the case of the U55C the ability to monitor the temperature of the High Bandwidth Memory (HBM). Of course once this foundation is created it is something we can build upon.
To get started creating this foundation, we can use the Alveo card management system example design. The first step in creating this foundation application is to download the XDC and board files from the Alveo webpage, these are available for each specific card. In this case we are going to download the files for the U55C.
Once these files have been downloaded, we need to store them in a location that Vivado can use. To do this the first step is to create a folder in a desired location and extract the compressed U55C board files into that directory.
With this completed we can open Vivado, I am using 2023.1 for this tutorial and select the location just created as a board repository. We can define this path from the Vivado setting and adding the directory just created to the Vivado Store, Board Repository.
After the board files have been installed we are able to create a new Vivado project targeting the Alveo card.
Following the creation of the project, we can create a new block diagram in IP integrator and add in the card management IP to IP Integrator. Select the CMS IP block under the design tab, right click and select open IP example. This will create a new project which contains the, card management subsystem reference design for the targeted Alveo. Once the example project is open we can close the initial project as we will not be using it further.
In the newly created example project, open the block diagram and observe the design. You will notice the PCIe/ DMA block, double clicking on this will show all of the necessary PCIe identification information all ready pre populated. Looking at the tabs you can also observe the settings for different elements of the PCIe configuration.
Examining the card management system design, you will also notice there is a MicroBlaze within the CMS subsystem. This MicroBlaze is not user configurable and the software is already associated with the MicroBlaze such that is included within the bitstream and begins operation once the FPGA has configured.
The ELF used by the MicroBlaze instance can be seen in the ELF association option under the tools menu.
As would be expected the resources required by the card management system are minimal as such the majority of the resources are able to be used by the application.
When it comes to programming the FPGA we have two options we can program the configuration memory or configure it using the JTAG USB. This JTAG USB is accessed by a USB micro connector on the external interface next to the QSFP+ connectors.
For this example to check it programmed OK I used the USB connection and using hardware manager was able to program the design into the U55C.
Now we need to write some software and get the AMD PCIe driver working to be able to work with the Card Management Subsystem from our x86 Host. We will look into this next time!
Workshops and Webinars
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and Petalinux
Arty Z7-20 Class looking at HW, SW and Petalinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with petalinux OS
Embedded System Book
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