Several times in recent blogs and posts on LinkedIn and Twitter I have mentioned that at Adiuvo we use a lot of RPI Pico’s for hardware testing and integration. We even also designed one in to the Space FPGA development board we recently developed.
Of course, the needs of the test equipment should be defined early in the project during the systems engineering phase. During this phase you should be identifying how each of the requirements is to be verified and at what level of the assembly. Verification might be by simulation, analysis, or test, of course while simulation is good for FPGA design there is no substitute for the real thing on hardware, aspects which simulation might not have accurately simulated come into play.
On several of our projects during development stages of the FPGA we have used RPI Picos to emulate the system, sensors, and communication interfaces. This is especially true for our space application development where we want to ensure the FPGA, responds correctly to failure conditions of equipment to which it might be connected.
Many space applications interface with high-speed interfaces such as ADC, DAC, Mass Memory Systems, and Image Sensors. Typically, these interfaces will have their own special to type test equipment developed.
However, connected to the FPGA are often several other sensors, actuators, clocks, signals, and communication interfaces. It is these interfaces which the RPI Pico can be of great use in testing at the hardware level.
The RPI Pico is very flexible in that it provides the developer with a range of commonly used embedded systems interfaces such as SPI, UART, GPIO, PWM and I2C. The real benefit however is the Programmable IO state machine (PSM), the PSM enables us to create both more complex and more deterministic interfaces. These include protocols and coding like Manchester(differential) Encoding, Generating Clocks, Regular Pulses.
To give some context to how they can be used for debugging I will explain a few use cases we have used them for at Adiuvo.
Clock Generation – Generation of 50MHz reference clock using the PIO, this enables different failure cases of the clock to be emulated stuck high low etc. This was used to help demonstrate a high reliability clock selection network which had to detect a platform supplied 50MHz and use it if present or switch to a local 50MHz if it was not present. Being able to control the clock stopping and starting easily from a PICO under terminal command was a great way to test the implementation on hardware of the clock detection and switching circuit.
Communications emulation – Emulation of a differential backplane bus, running a custom protocol to transfer configuration and reporting information between modules. The Pico could be configured to act as the master or a slave. This supported unit testing at card level where the master could be used to send commands to slave modules as they were commissioned. Similarly, Pico can be used in the slave configuration to ensure the master sends the sequence of commands it is expected to.
Communications Monitoring – Monitoring and logging communications across the backplane to debug and verify the communication sequence is as expected.
Sensor emulation – Emulation of I2C sensors across the system especially temperature sensors to enable modification of the reported temperatures while also being able to emulate failure modes.
Complex communications creation – Implementation of a space wire communication protocol between the FPGA and the Pico. This provides a simple interface which can be controlled over the USB communication.
Power management and monitoring – Monitoring the power network, to control, monitor and observe the dissipated power as the FPGA design is used for anger or in under testing for example beam line.
De-risking board bring up – Using dedicated test points to sensors, memories and peripherals enables micro python to be used to communicate with the peripheral. This enables us to leverage power of micro python to quickly test electrically the board assembly. An example of this is using the Rpi Pico I2C to communicate with RTC, SMBus components on the board as part of bring up.
Edge AI – Can be used for training and deployment of edge tiny ML models on the RP2040. This can be used for prognostics e.g. monitoring the currents, voltages and other parameters, this can be useful for training models which can be later deployed elsewhere e.g. within the FPGA. Whenever possible we try to use Edge Impulse for TinyML Edge ML Solutions.
The low cost of the Rpi Pico is also of a significant benefit as it means the cost of implementing the solution is low. This also makes it ideal for designing into hardware designs, like we did recently.