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MicroZed Chronicles: The Avnet ZUBoard 1CG

In early June Avnet announced the ZUBoard 1CG, as a compliment to the Ultra96V2 and MiniZed development boards and UltraZed and PicoZed and MicroZed SoMs. The ZUBoard 1CG contains the smallest of the AMD-Xilinx MPSoC Family the ZU1CG, the selection of which provides an ideal capability in the Avnet MPSoC / Zynq offering.

The current range of devices which ranges from the ZU7EV on the UltraZed-EV to the ZU3EG on the UltraZed-EG, Zynq 7020 / 7010 on MicroZed and Zynq 7030/7015 on the PicoZed. Of course, the smallest of them all is the Zynq 7007 on the MiniZed.


The ZU1CG on the ZUBoard provides the developer with dual core A53 processors cores, along with dual real time R5s in the processing system. Unlike in the EV and EG families within the CG family there is no Mali GPU. Logic wise the ZU1CG provides us with 81K logic cells, 216 DSP slices and 3.8 Mb of block RAM. These resource coupled with the interfacing capabilities of the board itself make it a great development platform for prototyping.


The main interface to the external world is three SYZYGY interfaces, these are connected to both the PS MIO, PS GTR and PL IO. This enables a wide range of SYZYGY boards to be connected to the ZUBoard for example ADC, DAC, DisplayPort and eMMC. Along with the main SYZYGY interfaces the ZUBoard also provides a MikroE Click interface which can be used to connect to a range of interface boards. To provide interfacing which is more standard in processing solutions the ZUBoard also provides USB 2.0 and 10/100/1000 Ethernet.


On board the ZUBoard provides on board temperature and pressure sensors, two push buttons, one each connected to the PL and PS along with switches (PS) Mono LEDs (PS) and RGB LED (PL).

When it comes to configuration the board can be booted from SDCard or QSPI and provides a JTAG UART for communication and configuration. Power-wise the board is powered by USB C which offers an elegant solution.


Lets take a look at how we can get up and going with the ZUBoard 1CG and get it to say hello world.


The first thing we need to do is create a new project, as we are targeting the ZU1CG part we need to use Vivado 2022.1. Select a project name and location and select a RTL project.


To get the board definition we can install it from the Xilinx Board Store as part of the project creation.

With the project defined click finish

With the project open, create a new block diagram and add onto it a Zynq MPSOC processing system and run the block automation.


Once the block automation is complete, open the Processing system block and take a look at the overall settings. These interfaces should align with the high level Avnet block diagram.

Taking a look at the Clock Configuration, you will see the R5, A53 clocks are running at 500 and 1200 MHz respectively.

The DDR Setting are also of interest, we have LPDDR4 running at 533 MHz.

We do not need to make any changes, close the re configuration dialog, connect the AXI Clock inputs to the PL clock output on the Processing System Block and generate the RTL Wrapper.


Once this has been completed we can, build the bitstream and export it to Vitis.


Within Vitis we can create a new application, I selected the hello world one and ran it on the board. (If you are not sure of any of the Vivado or Vitis Steps see these step by step guides here and here)

Running a simple program like this just allows us to pipe clean the process and check that the board is all OK. Now we can get started creating some projects and courses for the ZuBoard 1CG.


I am really impressed with the ZUBoard 1CG, there is a lot to like about it but, two of the most obvious things for me is the interfacing using SYZYGY along with the USB C Power interface making it easy to power in lab environments. I just hope the Avnet team have a PYNQ build planned for it also!

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1 Comment


Bryan Fletcher
Bryan Fletcher
Aug 10, 2022

Thanks, Adam! If people are interested in learning more about the AMD-Xilinx ZU1 device on the ZUBoard, please join us for a free webinar on September 1st -- https://pages.xilinx.com/EN-WB-2022-08-31-Registration_LP-Registration.html

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