MicroZed Chronicles: Debugging.
- Adam Taylor
- 7 hours ago
- 4 min read
Developing FPGA based solutions is a complex and presents many challenges which is why we spend a lot of time on the verification. During this verification we ensure that not only does the design implement the necessary functionality correctly, but also is capable of operating with the correct timing performance.
However, there are times during system integration when we need to debug on the hardware, for example to understand exactly a interfaces behaviour or hardware / software interaction.
Thankfully to do this we can use ChipScope and its integrated logic analyser, the ILA provides us with the ability to capture and analyse signals within the design at run time. Depending on the family of device we are targeting we are provided with two different options.
When we are working 7 Series and UltraScale(+) devices we can choose between two ChipScope elements, the ILA and the System ILA.
The ILA provides real-time hardware debugging capabilities by allowing users to set trigger conditions and capture signal data directly on the FPGA fabric. The ILA is able to capture signals with a range of interface definitions, from simple logic signals and vectors to AXI and AXI Streaming interfaces.
While The System ILA is an enhanced version that enables more comprehensive system-level debugging across multiple interfaces and clock domains. It provides capabilities for monitoring AXI interfaces, memory controllers, and other system interconnects.
The System ILA can capture longer trace buffers, support more complex trigger conditions, and monitor a greater number of signals simultaneously than the basic ILA. This makes it particularly valuable for debugging complex system-on-chip (SoC) designs, where multiple components interact with each other across different interfaces and protocols.
If we are working with devices in the Versal range, we can use the ILA with AXIS interface. The ILA with AXIS interface is similar to the System ILA provided in previous families. However the main difference is the connection to the debug hub. In Versal the debug hub connects via the AXI4 master interface of the CIPS (Configuration, Initialization and Power Management System) block to the debug cores using AXIS, where is in previous devices it was a custom interface.
As a result, a CIPS block must be present in the design to facilitate the AXI4 master connection to the debug hub.
When it comes to instrumenting with an ILA we are changing the actual design when the ILA is inserted. To ensure accurate and successful debugging we should have a clear and thought out process. I tend to use the process below, and only chance one parameter at a time when making changes to the design outside of inserting the ILA.
1. Create hypothesis for the issue which is being observed – break the project into small elements.
2. Instrument the design with an ILA.
3. Run the design with the ILA.
4. Analyse results against initial hypothesis.
When it comes to inserting the ILA into the design there are several methods we can follow.
1. Instantiate the ILA core using IP Integrator.
2. Identify signals for debugging in the RTL.
3. Insert the ILA using the debugger flow within the synthesis flow.
Along with just triggering and capturing data we can do several advanced features with the ILA. For example the trigger state machine enables us to perform advanced triggering. While we are also able to cross trigger between HW and SW by enabling the trigger ports.
The trigger ports enable us to trigger the ILA when a SW breakpoint is met or breakpoint the software when the ILA is triggered. This feature can be very useful when working with SW running on a A9, A53 or A72. I recently created a hackster.io project on how to debug and cross probe between HW and SW.
I also recently created a hacker.io project for debugging on AMD Versal devices, you can find it here.
In addition there are several aspects which should be considered, for example if you are working with Versal we can also use ChipScoPY. ChipScoPY provides a Python API which enables developers to work with the ILAs instantiated within Versal designs using Python. This opens up the wider python world when considering interaction.
We are also able to post process ILA results using Python as identified in this project.
The ILA is a powerful tool in our tool box, but please ensure you also do the verification first also.
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