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An Introduction to the Agilex™ 5 Series from Altera.

One of the things I love is exploring new FPGAs and SoCs, their capabilities and of course how to work with and get the best from the tool chain.


One FPGA / SoC which recently caught my eye is the Agilex 5 Range. The devices in the Agilex 5  range were announced across Intel FPGA Technology Days in 2022 and 2023. So over a series of blogs we are going to look at the Agilex 5, take a deep dive into some of its concepts and of course start working with a board and tool chain to create some simple designs.


Overview of Agilex 5 Series


At the heart of the Agilex 5 series are two distinct but closely related devices, the Agilex 5 D-Series  and Agilex 5 E-Series. The D-Series is developed with an emphasis on optimizing for both performance and size. This makes the D-Series an ideal selection for applications where performance is critical.  Conversely, the E-Series focuses on power and size making them ideal for application where size, weight, and power are constrained. Both the Agilex 5 D-Series and E-Series are fabricated on the Intel 7 Process.


Processing Capabilities


Both series are a System on Chip which provides the developer with heterogeneous processing solutions. This heterogeneous solution provides dual core Arm Cortex A55, 64 bit processors are capable of operating at up to 1.5 GHZ. The second processing element is dual core Arm Cortex A76, 64 bit processors which are capable of operating up to 1.8 GHz. Each processor has Instruction and data caches, level 2 cache and a shared 2MB level 3 cache.


As  one would expect with for a processing solution these processors cores are connected to via an interconnect to the a range of peripherals which range from standard slow speed peripherals such as I2C, SPI, I3C and GPIO to high speed peripherals such as USB 3.0, USB 2.0 and Ethernet.

Of course to enable execution of the application in the HPS, the  memory controllers support DDR4, DDR5, LPDDR4 and LPDDR5.


FPGA Fabric and Architecture


Connectivity between the HPS (Hard Processor System) and FPGA Fabric leverages AXI Interfaces, enabling high bandwidth transactions. The FPGA fabric leverages the second generation of the Intel Hyperflex Core Architecture. If you are not familiar with the Hyperflex architecture, it is designed to enable higher throughput by enabling a higher core clock frequency. The key innovation in the hyperflex architecture is a re architecting of the routing multiplexer to provide an optional register stage.

This inclusion of the hyper-register is automatically performed by the implementation tool, to achieve the maximum core clock frequency.


Along with the next generation of hyperflex routing the Agilex 5 devices also include an updated Adaptive Logic Module (ALM). One of the key elements of this is the eight input LUT, this LUT can be fractured to implement two four input functions. As would be expected Quartus Prime leverages the capabilities of the ALM to implement the highest performance implementation.


In addition to the ALM, the Agilex 5 devices also introduce a variable precision DSP (Digital Signal Processing) which is capable of implementing a range of functions from 27x27 multiplication to implementing AI Tensor blocks supporting INT8 operations.


Interfacing and IO Capabilities


When it comes to interfacing with the wider world outside of the device in addition to gigabit serial transceivers which support data rates of up to 28.1 Gbps we are provided two IO bank classes HSIO and HVIO. High Speed IO (HSIO) provides 96 IO per bank, and is capable of supporting LVCMOS 1v2 to 1v0, TDS , SGMII and MIPI DPHY.  While High Voltage IO provides 20 IO per bank and support LVCMOS between 3v3 and 1v8 at data rates between 125 MHz and 100 MHz depending on the exact IO bank voltage used.


Security Features


As you would expect the device security is also well considered with the Secure Device Manager (SDM). We will look at the SDM in depth in a future blog, however the SDM provides developers with a Secure boot, key management and anti tamper features. Capabilities which are increasingly important for devices deployed at the edge as the Agilex 5 in intend.


Now we have a basic introduction to the Agilex 5 D and E series we will be looking in our next blog at more in depth elements of the architecture.

 If you want to learn more about Agilex™  FPGA portfolio please visit Altera webpage

Embedded System Book   

Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.

Sponsored by Altera


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