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Writer's pictureAdam Taylor

Altera Agilex 5E Premium Development Kit and NIOS V

In our last instalment we configured the tool chain and started the creation of the example design for the Agilex 5E Premium development kit. This is a good starting point as it provides us with a NIOS V processor implemented in the logic.

This example acts therefore as a great starting point for custom developments. When we created the reference design we are able to select the type of NIOS V processor and the on chip memory size. For this example I selected the NIOS V M which is a microcontroller configuration of the NIOS V processor configured to work with real time operating systems. The 128 KB On chip memory size is to ensure the compiled program is able to be stored within.

 

Walking through the project creation wizard enables us to select the Agilex 5E premium development kit.

Once the project is opened we can open Platform designer to explore the design which is implemented. Here we will see the NIS V M processor system has been configured with the following

 

  1. On Chip Memory – This holds the application and data

  2. IO PLL – This generates the clocking required for the NIOS V sub system

  3. PIO – Programmable IO  enables the IO to interact externally

  4. NIOS V M  - Configured with debug

 

This is shown clearly in the diagram below.

Initially we do not need to make any changes to the development, the next step is to generate the application code for inclusion within the OCM.


To do this we will need use the NIOS V shell and we will leverage the Quartus Prime Pro project and platform designer to create a board support package and application.


The board support package (BSP) will provide all of the necessary hardware abstraction level (HAL) library files to support software development on the NIOS V M target.


The first step in this process is to create a BSP which we can do by running the niosv-bsp command in the shell.


To generate the BSP we need to provide the location of the Quartus project and platform designer file. We also need to select the location of the output BSP.


As the example design provides us with a refence C application file customised for the specific NIOS V instantiation we select.  


I will store the BSP under the same root directory.

With the BSP created the next step is to create the application and the cmake lists in this case we are using the reference application provided by the example design.

With the application and BSP cmake text files created, the next step is to create the cmake files.   

Once the cmake files have been completed we are able to build the application elf.

Following compilation the ELF will be available and we are able to convert the elf into a hex format for inclusion within the Quartus Prime Pro build.

To do this we need to update the platform designer OCM memory to include the hex file when the FPGA is recompiled.

Alternatively we could use the Ashling RiscFree IDE to download and debug the application running on the hardware. We can do this by importing a NIOS V project created using the niosv shell using the import niosv project option.

Once we have the design loaded onto the board we can connect and use the IDE to download and debug the application.

Not only have we created our first project on the Agilex 5E development kit, but we have also created an NIOS V solution with which we can expand as required by out application.


Embedded System Book   


Do you want to know more about designing embedded systems from scratch? Check out our book on creating embedded systems. This book will walk you through all the stages of requirements, architecture, component selection, schematics, layout, and FPGA / software design. We designed and manufactured the board at the heart of the book! The schematics and layout are available in Altium here   Learn more about the board (see previous blogs on Bring up, DDR validation, USB, Sensors) and view the schematics here.



Sponsored by Altera

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