Over the last two months, I have had several clients approach me for help regarding DDR3 / DDR3L interfaces that they have connected to...

One aspect of FPGA design that we haven’t really examined is multi-gigabit transceivers (MGT). These transceivers are available in many...

One of the big advantages of the Kria SoM is the ease with which new applications can be created, either around the existing applications...

One of the most common requests I get via my consultancy is about the RFSoC and how its capabilities can be leveraged. If you haven’t...

A couple of weeks ago I was working to bring up the sensors connected to the I2C and SPI interfaces on the custom SensorsThink Smart...

I use PYNQ a lot and one of the things I have been meaning to blog about is how it interacts with hardware. Whether it’s a custom overlay...

First look at the Xilinx Kria SoM portfolio, including features and pricing. Watch my exclusive interview with Xilinx on the new products.

With the Vivado application completed, we can export the XSA with the BIT file into a Vitis project.

In a previous installment, we looked at the Trenz ZynqBerry Zero. Let's create a simple image processing system using the MIPI input.

In this blog, we will explore how to validate a custom Vivado configuration on a Zynq board.

You may have seen my previous posts referencing a book I’ve been writing over the last two years with Dan Binnun and Saket Srivastava on...

I thought it would be a good idea to outline a few of the available debug options for when your Zynq-7000 doesn't boot as expected.

For this first Versal blog, let's take a look at how to get a bare metal program up and running so that we can say "hello world".

This blog explores the PYNQ image for the TySOM-3A-ZU19EG, the largest device in the Xilinx Zynq UltraScale+ MPSoC range.

In this blog, we are going to examine how we can create a simple kernel application and then complete the rest of the host application.

As I mentioned in last week’s blog, I want to spend some time discussing OpenCL because being able to work with OpenCL is going to be an...

The ability to work with OpenCL at higher levels of abstraction is increasingly important for FPGA developers. We can use OpenCL to...

Silexica has released a plugin for Vitis HLS 2020.2 that adds a new pragma that performs loop interchange.

I thought I would examine how we can implement safe state machines when using Vivado 2020.2 and Xilinx synthesis