MicroZed Chronicles: Using Analysis View in Vitis and Vivado
One of the most useful views available in both Vivado HLS and Vitis HLS is the analysis view.
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ADIUVO ENGINEERING BLOG
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Adam Taylor
- Nov 4, 2020
- 3 min
MicroZed Chronicles: AXI Stream Verification IP
The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.
Adam Taylor
- Oct 19, 2020
- 4 min
Using SLX FPGA in Vitis bottom up flow
Last year, I examined SLX FPGA and used it to optimize IP Cores for implementation in Vivado looking at security and industrial algorithms.
Adam Taylor
- Oct 7, 2020
- 3 min
MicroZed Chronicles: A look at the new Trenz TE0802
I recently received the new Trenz TE0802 development board, designed and manufactured by Digilent partner Trenz Electronic.
Adam Taylor
- Sep 30, 2020
- 4 min
MicroZed Chronicles: Vivado Simulator Interface – Using C Test Benches on HDL
For complex algorithms, it is often a good idea to first create a model which defines the algorithm’s behavior.
adam@adiuvoengineering.com
- Sep 23, 2020
- 4 min
MicroZed Chronicles: Introduction to RTL Simulation and XSIM
No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...
Adam Taylor
- Sep 16, 2020
- 3 min
MicroZed Chronicles: RTL Design Verification Techniques
So, before we look in more detail at Vivado XSIM, let’s first understand the entire verification landscape and what we are trying to achieve
Adam Taylor
- Sep 9, 2020
- 3 min
MicroZed Chronicles: UltraFast Design Methodologies
Using Xilinx UltraFast design methodologies can offer significant benefits when implementing designs.
Adam Taylor
- Sep 2, 2020
- 3 min
MicroZed Chronicles: Quality of Result
In this blog we explore the Quality of Result Assessment (QoRA) and Quality of Result Suggestions (QoRS).
Adam Taylor
- Sep 1, 2020
- 3 min
How to Install Vitis
This blog will break down step-by-step how to download and install the Vitis IDE from Xilinx.
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