Recently, I have posted a few blogs and projects which looked at signal processing or filters. I thought it would be a good idea to go...

Having learned in our previous blog about how the Base Address Registers work for transfers in the Alveo system, we are now able to start...

Readers of the blog will know I am a huge advocate of System on Modules (SoM) like the K26, MicroZed, PicoZed, UltraZed and of course the...

One of the questions people often ask me is how to get started on the journey of learning about FPGAs. Of course, everyone’s journey is...

In the 2024 MicroZed Chronicles, we are going to examine Versal in depth with a particular focus on the AI Edge series. We’ve looked at...

In our last blog we discussed an E Ink / ePaper driver that I had designed. Today we are going to discuss how to integrate it with a Zynq...

Developing FPGA solutions can be a challenge and as a consultant, I often see designs which are facing difficulties late in the...

I remember being sat in the crowd at Xilinx Developer Forum 2018 (XDF18) when Xilinx CEO, Victor Peng announced upcoming Alveo PCIe based...

If you’ve been working with Vitis 2023.1, you’ll already be aware that a new Vitis Unified Integrated Design Environment (IDE) was...

We have created projects and blogs on most AMD families over the years but have never created one for the Artix UltraScale+ (AUP) FPGA....

Developing complex systems is a risky business; around one third of all complex engineering projects will fail; two-thirds of engineering...

Last week we looked at how we could use spidev and I2Cdev to work with devices which use SPI or I2C interfaces. These are commonly used...

Regular readers of this blog and my Hackster projects will note that I tend to use either bare metal applications or PYNQ when developing...

Adiuvo are looking for a graduate engineer to join our awesome team to help develop FPGA, Embedded Software and Electronics. About Adiuvo...

Last week we looked at how we could use 7 series clocking resources to provide integer clock division without using MMCM. In this week’s...

Many of our FPGA designs are multi-clock, meaning several clocks within the design, which can introduce clock domain crossing challenges....

In September 2013, I was about to start a new role, as head of electronics at a space imaging developer when what should arrive in the...

A couple of weeks ago I was emailed about how to get the ethernet working on the Digilent Arty A7 development board. We have covered this...

Over the years working as both a FPGA developer and author of this blog, I have found it very useful to have a range of test equipment....