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In a previous installment, we looked at the Trenz ZynqBerry Zero. Let's create a simple image processing system using the MIPI input.

In this blog, we will explore how to validate a custom Vivado configuration on a Zynq board.

You may have seen my previous posts referencing a book I’ve been writing over the last two years with Dan Binnun and Saket Srivastava on...

I thought it would be a good idea to outline a few of the available debug options for when your Zynq-7000 doesn't boot as expected.

For this first Versal blog, let's take a look at how to get a bare metal program up and running so that we can say "hello world".

This blog explores the PYNQ image for the TySOM-3A-ZU19EG, the largest device in the Xilinx Zynq UltraScale+ MPSoC range.

In this blog, we are going to examine how we can create a simple kernel application and then complete the rest of the host application.

As I mentioned in last week’s blog, I want to spend some time discussing OpenCL because being able to work with OpenCL is going to be an...

The ability to work with OpenCL at higher levels of abstraction is increasingly important for FPGA developers. We can use OpenCL to...

In this post, we will expand the use of GHDL with an open-source verification framework for VHDL called UVVM.

In this blog let's look at how to install GHDL and use it to simulate our VHDL designs.

Silexica has released a plugin for Vitis HLS 2020.2 that adds a new pragma that performs loop interchange.

I thought I would examine how we can implement safe state machines when using Vivado 2020.2 and Xilinx synthesis

The Trenz ZynqBerry Zero is in the same form factor as the Raspberry Pi Zero, but with a Zynq Z-7010. Let's take a closer look.

I need an entry-level scope for a project I am working on so I decided I would pick up a Tektronix TBS1052C and take look at what is inside.

One of the most useful views available in both Vivado HLS and Vitis HLS is the analysis view.

This past summer, I was lucky to present several detailed virtual workshops on Vivado, PYNQ, Vitis, and more. They are available on-demand.

The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.

The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped

I recently received the new Trenz TE0802 development board, designed and manufactured by Digilent partner Trenz Electronic.