MicroZed Chronicles: Free Virtual Workshops On-Demand
When it comes to developing for Xilinx FPGA and heterogeneous SoCs, the ability to work effectively with Vivado, Vitis, and PYNQ is key. Regardless of our level of experience as developers, it is always good to refresh our skills and keep learning about the tools and devices.
This past summer, I was lucky to present several detailed virtual workshops on Vivado, PYNQ, Vitis, and more. For readers who did not see them the first time, these courses are available to watch on-demand and all supporting lab books and materials are posted online.
Introduction to Vivado
This three, one-hour session covers project creation, simulation, IO constraints and timing constraints creation, along with investigating and correcting timing issues. The final session of the tutorial walks through packaging IP and working source control along with recreating the project.
No board required. All the labs are contained within Vivado.
Implementing Arm Cortex-M1 and Cortex-M3 Processors in Xilinx FPGA
This lab is based upon Vivado 2018.3 and walks through the Arm Cortex-M1 and Cortex-M3 processors. Along with an introduction to the M1 and M3 processors, the labs details step-by-step instructions on how to get the Arm reference design up and running. It also shows how to modify the design to include PMOD sensors and generate the necessary files for programming the FPGA.
The target board for this application is the Digilent Arty S7-50 however; it can be implemented in any Xilinx FPGA or SoC.
Introduction to PYNQ
In these three, one-hour sessions, we walk through all aspects of PYNQ (Python for Zynq) beginning with working with the base and logic tools overlays to learning how to install overlays available in the PYNQ community. The second and third sessions explore how to create your own overlay using Vivado, IP Integrator, and IP from the PYNQ and Xilinx libraries. This culminates in the creation of a bar code decoding application using an external HDMI camera.
The target board for this lab is the TUL PYNQ-Z2, although it can be adapted for any PYNQ board.
Getting Started with Vitis
This two-hour session focuses on how to create accelerated applications using Vitis and covers project creation, software, and hardware emulation along with co-simulation in Vivado. The session also shows how to use Vitis Analyzer and Vitis HLS to optimize the accelerated application. Finally, the session concludes by demonstrating how to implement a Vitis-AI DPU so that the designer has the tools required to start working with Vitis-AI and accelerating AI applications.
This lab series is designed for the Avnet Ultra96-V2 and the Xilinx ZCU104 and Alveo U50 boards from Xilinx.
Motor Control with the MiniZed
This three-hour lab details how to implement a simple motor control application using the MiniZed. While this is a simple application, it shows how we can easily interface with motors and sensors etc. using programmable logic. This three-part lab discusses everything needed to create the design in Vivado and Vitis.
The target board for this course is the Avnet MiniZed.
But wait, there is more!
If you want to learn about high-reliability design, I recently gave a one-hour webinar on the challenges and issues that come up when creating these systems and how we can design our embedded systems and FPGA to be robust.
To access some of these resources you might need to register with for free with online communities such as Hackster.io or Element14, both are great communities for engineering and hardware enthusiast resources.
Please also pay attention to the version of Vivado in these labs/workshops (especially the Arm Cortex-M1 and M3 lab which requires Vivado 2018.3). If you have any issues reach out to me at email@example.com.
Over the next year, I plan to create more content like the above and I would love to hear your thoughts and comments about what interests you. Comment on this blog with your ideas! I have PetaLinux, high-level synthesis, and image processing in mind but would like suggestions for what you would like me to cover in the future.