To kick off this new year of blogs, I want to build upon the verification blogs previously started and examine how we can use VHDL frameworks such as UVVM. UVVM requires VHDL 2008 commands not currently supported by the Vivado Simulator so this leaves us with the choice of using either a commercial simulator such as ModelSim or an open source simulator such as GHDL.
As such, in this blog we are going to look at how to install GHDL and use it to simulate our VHDL designs. GHDL has been around for a several years, first released in 2002, and provides VHDL analysis, compilation, and simulation. What makes GHDL different to other simulations is that it compiles the VHDL into machine code by using one of several backends like GCC, LLVM, or its own internal mcode compiler. GHDL will run across Linux, Windows, and MAC platforms. I will be using a Windows instantiation for this example.
GHDL does not currently include its own waveform viewer so we will also be installing the GTKWave in order to view and debug the design under test.
Installing GHDL is remarkably simple. We first need to download the GHDL version for our specific operating system. The specific OS version can be downloaded from the GHDL GitHub release page. If you are unsure which version you need from the release page, see the readme documentation.
Once the selected file has been downloaded, the compressed file needs to be extracted to a location where we want GHDL to be installed. GHDL is a command line tool and needs to be added to the environment variables so that its executable location is known.
To be able to view the waveforms produced by GHDL, we also want to install GTKWave which can be downloaded from this link. Again, installation of GTKWave is straightforward and involves extracting the compressed file to the desired directory and adding an environment variable.
Getting started with GHDL to run and simulate a VHDL is a three-stage process:
Analysis - This compiles the file or files and has several attributes which can be applied, ranging from debugging information to the standard of VHDL used by the compiler. The output of the analysis stage is the object file which can be used later for elaboration.
Elaboration – The elaboration stage re-analyses the VHDL files and creates the necessary configurations in line with the Language Reference Manual.
Run – This stage executes the simulation.
There are additional commands which can be run including performing a syntax check that analyses the file without generating the compiled code.
To demonstrate how we can work with GHDL and GTKWave, I will be using the RTL code and test bench to create the finite state machine in a previous blog.
Place the RTL and test bench within the same directory.
We can then open a command window along with the analysis, elaboration, and simulation. Once the command window is open, change the directory to the location of the test bench files.
We do this using the following commands:
ghdl -a fsm_full_case.vhd ghdl -a fsm_tb.vhd
The above commands will run the analysis and create the compiled machine code.
ghdl -e fsm_tb
Notice how when the elaboration is called, we call the test bench only.
ghdl -r fsm_tb –vcd=sim.vcd ghdl -r fsm_tb –wave=sim.ghw
Finally, we can run the simulation and save the waveform output as either a VCD or a GHdl Waveform (GHW). The difference between the VCD and GHW files is that the VCD file is Verilog based and contains only a limited number of VHDL signal types and does not include enumerated types. The GHW file can be written and includes all the signals in the design, including enumerated types.
In the diagram above, you can see the compilation of the two VHDL files along with the elaboration of the test bench, followed by the creation of the VCD. If a GHW file is required, we can export it by using the command above.
To view either the GHW or VCD file, we can use the same command terminal to load up the VCD/GHW using the command below.
Gtk <file name.ghw/vcd>
When used to load a VCD file, the image above can be observed which includes most of the design signals. The images below shows the GHW file when it is loaded. Note the additional signals which include the state machine enumerated type transitions in the waveform.
We can run simulations of our VHDL designs now that we have GHDL up and running. This also means we are able to start looking at verification frameworks such as UVVM.