One of the game changing elements of the announcement from Rapid Silicon was that the entire tool chain would be based on open-source tools. This is particularly exciting because it will enable developers to go from design capture to bit stream generation using open-source tools.
I just joined the Rapid Silicon early access program and over the next few blogs will be looking at the tool chain in a little more depth. In this blog we are going to take a high-level look at each element of the tool chain.
Raptor, like many EDA tools, is based around TCL/TK which enables automation, scripting and CLI control of the implementation. If you prefer to work with a GUI and not the command line FOEDAG is provided to create a QT based framework. Within FOEDAG we can of course still use TCL as required within the FOEDAG environment.
Generation of modern FPGA designs also requires access to large IP repositories along with the ability to integrate the IP quickly and efficiently. One of the most popular open-source frameworks for integrating IP is LiteX. LiteX was developed by Enjoy-Digital to create client projects and supports a range of Buses and Interconnects as well as provides simple and complex IP cores ranging from UART to PCIe, and SATA along with support for a number of soft- and hard-core CPU. LiteX systems are described using Migen, which allows integration of Verliog, VHDL and Spinal HDL modules along with Migen.
To implement the design captured using FOEDAG and LiteX open-source synthesis and implementation tools are provided.
Synthesis is provided by the well-known YosysHQ created by Claire Wolf (of course YosysHQ needed updating to include support for Rapid Silicon devices and, as such, Rapid Silicon has invested strategically in YosysHQ).
Once the synthesized netlist is available for place and routing VPR (Verilog to Routing), started by Vaughn Betz at the Univ. of Toronto is used to perform implementation and bitstream generation.
VPR is used not only to generate the place and route of the design, but it was also used in the tape out of the silicon device as from its inclusion within the OpenFPGA framework. OpenFPGA is a very interesting framework as it introduced an XML based architecture definition which describes a complete FPGA fabric. This XML based architecture description allows the Configuration Protocol, Interconnect, Technology Library and Circuit Library along with all the other elements necessary to define a complex FPGA architecture.
Generation of the bitstream is never the final element of a design, we also need to ensure the timing performance of the implemented design is acceptable. This is typically performed by Static Timing Analysis (STA), In the case of the Rapid Silicon open-source tool chain the STA is performed by OpenSTA.
Long before we implement the design we should also perform simulation to verify the performance of the design captured. There are several open-source simulators available but one of the most popular is Verilator which enables simulation of Verilog and system Verilog. Verilator compiles the RTL into C++ or SystemC enabling a faster run time of the simulator especially as it supports multithreading.
To support the RISC-V 32-bit embedded application processor within the first of the Rapid Silicon Gemini devices Andes IDE / SDK is used. Andres IDE/SDK is eclipse based so it should be familiar to many engineers already working with soft / hard embedded processor cores in programmable logic devices.
Looking at this tool chain it is exciting, for many years the FPGA community has been pushing for an open-source approach. Indeed, many of the tools which form part of Raptor have been around for several years and have enabled developers to create FPGA designs via reverse engineering. Raptor for the first time is an open-source tool chain for FPGA and programmable SoC which not only has an open-source tool chain but in which the device manufacturer is playing an active part in not only supporting the tools, but actively developing and working with the tools creators.
I have just received the first drop of the Raptor tool chain so I am looking forward to creating my first application and testing out the tool flow and learning the tool chain.
This is going to be an exciting journey!