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Meet Rapid Silicon: Open-Source FPGA and Toolchain

Updated: Jun 23, 2022

One of the most common requests in the FPGA community is for open-source tools. Enter Rapid Silicon who recently announced their Gemini devices. Rapid Silicon’s devices are not only based upon an open-source FPGA architecture but will also be developed with an end-to-end open-source tool chain called Raptor.

Rapid Silicon Test Chip

So who is Rapid Silicon? Let’s start at the beginning. Rapid Silicon was founded in 2020 by chairman and CEO Dr. Naveed Sherwani. Dr. Sherwani has an excellent pedigree in the Semi-Conductor industry, having previously been the President & CEO of Si-Five and is currently chair of the Open-Source FPGA Foundation. Around him he has gathered an executive team with over 150 years’ combined experience in the FPGA and Open-Source FPGA. On the team are some familiar faces that I’ve had the pleasure of collaborating with through the years. Hear for yourself a bit more about the company from Dr. Sherwani himself in this video:

Rapid Silicon has been busy over the last 2 years and just announced their first device family, code named "Gemini", which technically is a heterogeneous system-on-chip. Inside Gemini we find not only FPGA fabric, but also dual core A53 application processors, a RISC-V 32 Bit embedded application processor, a DDR controller which supports DDR4 at 1066 Mbps and standard interfacing peripherals such as UART, I2C, QSPI, GIGE and USB2. For high-speed communications on and off chip 16.3125 Gbps SerDes are provided. Interestingly this is all connected internally over a network-on-chip, called the FlexNoC. Fabricated on a 16nm node from TSMC, Gemini devices will offer developers between 50-75K Logic Elements (which are built on the Open Standard), a 6 Input LUT structure and up to 400 I/O.

Within the FPGA fabric we will find not only CLBs but also 18Kb Dual Port RAMs, and DSP blocks.

We will look more in depth at the architecture in future blogs, but the methodology adopted by Rapid Silicon for development of the initial range of devices is very interesting. It is built around three pillars:

1. Use of Open FPGA to design the core fabric

2. Utilisation of industry standard 3rd party IP libraries

3. Development of FlexNOC, enabling easier IP integration in the silicon to support future products and variants.

Software is where it gets exciting with the Rapid Silicon Raptor tool chain, which is based significantly on open-source technology. Everything from design capture, to IP management, and implementation from synthesis to bitstream is based on open-source tools. The tool flow does include some provision for OEM tools with design entry language reference manual parsing achieved through Verific, which is industry standard and provides options for either commercial or open-source synthesis tools.

The same choice of either an open source or commercial tool chain is also available for verification where developers can use either Verilator or Riveria-Pro. However, implementation and bit stream generation use primarily open-source tool chains where Rapid Silicon have engineers contributing back to these projects as adaptions are made to support the Gemini architecture and implementation.

Rapid Silicon’s first test chip has been delivered and brought up; I cannot wait to explore their technology in more depth and share with you all. Stay tuned!

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