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MicroZed Chronicles: JTAG using a Raspberry Pi Pico

I’m a big fan of the Raspberry Pi Pico with the RP2040 microcontroller and have used it several times to emulate system interfaces on my FPGA developments. I was, therefore, very interested when I saw a release of a Xilinx virtual cable application on r/FPGA a few weeks ago. This uses the RPi Pico and allows the RPi 2040 to act as a JTAG adapter for Xilinx FPGAs. Many development boards have built-in USB JTAG. Some SoMs, however, do not because a JTAG programmer is required.

The RPI Pico costs around $4 which makes it a very low-cost solution. I thought I would check out if it worked and if there were any limitations in conjunction with the MYIR Z-turn board. (Spoiler alert: it worked!) I selected the MYIR Z-turn board for a couple of reasons, not the least of which that its JTAG header was on .1 inch pitch headers which makes for an easy connection with RPi Pico.


To get started, I used a Linux virtual machine that had Vitis / Vivado 2020.2.2 installed. I first installed the dependencies on the virtual machine as outlined by the GitHub instructions, then made a new repo directory and cloned the pico-SDK and the XVC-Pico projects.


Once the repos are cloned, we can build the host-side daemon. This runs on the Linux development machine and the image for the RPi Pico. We do this by following the instructions provided in the GitHub.

Once the daemon is built to use the XVC-Pico, we need to start it running on the development machine.

To download the image to the RPi Pico once the UF2 file is available, hold the bootsel boot down as the RPi Pico is powered up and the board will mount in your file system. Simply copy the UF2 file and it will be installed and ready to go.


With the RPi Pico programmed, we can connect the GPIO that is used to provide the JTAG signals to the JTAG signals on the MYIR Z-turn board. Be careful when doing this. With other boards like the GPIO, the RPi Pico is 3v3 so you need to make sure the target board provides 3v3 to Bank 0 otherwise there is a risk of damaging the Zynq device.

Make sure you connect a ground reference between the Pico Pin 23 and the target board. You are not going to be able to connect to the device otherwise because the signals are not correctly referenced with respect to each other.


With the daemon running and the boards connected and powered on, we can start Vivado and attempt to open Hardware Manager to connect to the board.


Open Hardware Manager when Vivado starts and create a new hardware target. Use the Xilinx Virtual Cable (XVC) option. Use the IP address of the Linux development machine when prompted for the XVC.


I was pleasantly surprised when I added the XVC and the device on the Z-turn was detected.

The next step was to read the XADC temperature and voltages using the hardware manager. Again, the values were displayed as I expected. This should mean ILAs are also able to be supported in the hardware.

The final test was to see if I could download and debug a simple C application running on the Zynq Processing System.


Creating a simple program in Vitis to run hello world and then downloading the application using the debugger was straight forward. I did leave the hardware manager open and connected in Vivado also though.

On the Z-turn board, I was able to download and single step through the application.


Overall, I am impressed with the XVC-Pico application and there are several interesting use cases for low-cost solutions in cost optimized developments.


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