MicroZed Chronicles: FPGA Horizons London: AI, Security and the Future of FPGA Engineering
Yesterday marked the second FPGA Horizons London, held at the Pullman Hotel, and what an incredible event it was.
Having turned away nearly 200 people when I ran the first event last year, I decided to be a little more ambitious this time and booked the entire facility, including the Shaw Theatre, which seats 450 people.
To put that into perspective, FPGA Horizons London 2025 attracted 290 attendees, 28 exhibitors and 21 speakers. Looking around the venue again yesterday, I am still not quite sure how we managed to fit everyone in last year!
On the evening of day one, someone asked me in the bar why I started FPGA Horizons.
The simple answer is that the UK did not have an FPGA conference.
The longer answer is that I love FPGAs and the ecosystem surrounding them. I want to ensure we have opportunities to share ideas, keep up to date with the latest developments and, perhaps most importantly, inspire the next generation of engineers, especially FPGA engineers.
I certainly did not start FPGA Horizons to make money, far from it. I started it because I wanted to give something back to an industry that has given me so much.
Two years in, what makes me proudest is that FPGA Horizons still feels exactly as I hoped it would, a community of FPGA engineers coming together.
Throughout the event, the exhibition spaces were full of engineers talking, exchanging ideas, discussing challenges and engaging with exhibitors.
That, for me, is what FPGA Horizons is all about.
Over the next few weeks, we hope to share the presentation slides and recordings from the conference. In the meantime, I wanted to reflect on some of my favourite moments and the technical themes that stood out.
The Keynote: System-Level Design Meets AI
The opening keynote was delivered by my good friend Kirk Saban, AMD's Corporate Vice President for Embedded Products, Software and Solutions.
Kirk explored system-level design and AI-driven engineering workflows, highlighting an important shift in how we approach embedded system development.
Traditionally, we have often started with a device and worked out how to fit our application into it. Increasingly, however, the starting point is the workload itself. From there, we determine the most appropriate combination of programmable logic, embedded processors and heterogeneous computing resources to deliver the required performance.
This is an important change in mindset, moving the emphasis away from individual devices and towards the architecture of the complete system.
The second half of Kirk's keynote introduced AMD's new Ross agentic AI technology.
Ross is intended to help engineers architect, implement and optimise their designs using AI-assisted workflows. The central idea is that the engineer remains the architect of the solution, while AI helps with implementation challenges, timing closure, debugging and other aspects of the development process.
What makes Ross particularly interesting is that it is not confined to the traditional AMD FPGA and SoC development environment of Vivado and Vitis.
It also encompasses ROCm and Ryzen software capabilities, enabling engineering workflows that extend across FPGAs, SoCs and embedded x86 platforms.
For me, this raises some interesting questions about how our roles as FPGA engineers will evolve. As AI becomes increasingly capable of assisting with implementation and debugging, the ability to understand workloads, make architectural decisions and evaluate system-level trade-offs will become even more important.
The engineer remains central to the process, but the tools available to us are changing rapidly.
Kirk's keynote established two themes that would recur throughout the conference: how we design our systems and how we secure them.
In keeping with our ambition to make FPGA Horizons a place where engineers can learn about emerging technologies firsthand, day two also saw AMD deliver the world's first Ross lab, with 100 conference attendees having the opportunity to explore the technology.
Security Was the Story of the Day
If AI was one of the major themes of FPGA Horizons London, security was undoubtedly the other.
With the emergence of the EU Cyber Resilience Act (CRA), security is becoming an increasingly important consideration for anyone developing electronic products, including those based around FPGAs and SoCs.
Several speakers approached the subject from different perspectives, demonstrating just how broad the challenge of securing modern embedded systems has become.
Matt Holdsworth from Lattice began with the fundamentals of security, framing the discussion around trust, privacy, integrity and availability rather than immediately diving into cryptography.
Ian Pearson from Microchip explored the EU Cyber Resilience Act and its implications for both new and legacy products entering the European market.
Graham McKenzie from Altera examined security from the device perspective, including the challenges of preparing for a post-quantum world.
Nick Theisejans from TÜV Informationstechnik provided an evaluator's perspective on why FPGAs can be particularly difficult to certify, especially when we can no longer assume that an attacker will not have physical access to the hardware.
Valtteri Allekotte from Xiphera proposed a common framework for implementing an FPGA-based hardware root of trust.
What struck me was how the presentations collectively demonstrated that security can no longer be treated as an additional feature or something considered towards the end of development.
It needs to be part of the architecture from the beginning, encompassing everything from device selection and hardware trust to system implementation, certification and long-term product support.
The conference closed with a fascinating presentation from Dirk Koch of Heidelberg University, entitled Some Don't Like It Hot.
Dirk demonstrated how a design could concentrate more than 100 W of power dissipation into just one percent of an FPGA die, accelerating device ageing. He also discussed how his research group had planted a denial-of-service attack on a major cloud FPGA provider.
It was a remarkable demonstration of how hardware-level behaviour can be exploited and a reminder that FPGA security presents challenges extending well beyond conventional software vulnerabilities.
A thought-provoking way to close the technical programme.
Beyond AI and Security
Of course, FPGA Horizons would not be FPGA Horizons without a broad range of practical engineering presentations.
Outside the AI and security themes, the technical programme covered everything from HyperRAM and LPDDR4 interfacing to standardised pinouts for System-on-Modules (SoMs).
One of my personal favourites was Bryan Fletcher's presentation on breaking out and routing 0.5 mm pitch devices, including the engineering challenges involved in developing the Explorer board.
These are exactly the kinds of practical engineering discussions I love seeing at FPGA Horizons. There is always something to learn from the design decisions, compromises and lessons encountered when turning an idea into working hardware.
And speaking of the Explorer board, a limited number are now available for pre-order on my merch store.
Exploring the Explorer Board
The demonstrations covered a range of applications, including SYZYGY interfacing for image processing and ADC sampling, along with IBERT eye diagrams using the TR4 SYZYGY interface.
One of the things I particularly enjoy about the Explorer project is being able to demonstrate real hardware, discuss the design decisions and show what is possible with the platform.
Seeing engineers engaging with the demonstrations, asking questions and exploring potential applications was another highlight of the event.
Issue 5 of the FPGA Journal
FPGA Horizons London also provided the opportunity to release issue 5 of the FPGA Journal.
This issue includes my thoughts on how we should approach working with AI as engineers, along with the results of our long-awaited FPGA salary survey.
Both are subjects I think are particularly relevant to the FPGA community as we consider how the industry, our tools and our careers are evolving.
You can find the latest issue online.
Looking Ahead
All told, FPGA Horizons London was an excellent event, and I am already looking forward to doing it all again.
There is a tremendous amount of work involved in organising a conference like this, but seeing the community come together, exchange knowledge and form new connections makes it worthwhile.
The FPGA industry has always been built around engineers solving difficult problems, sharing their experiences and pushing the boundaries of what is possible. FPGA Horizons is my small contribution to helping that community continue to grow. And we have plenty to look forward to.
First, FPGA Horizons heads to the United States in late April, before returning to London in early October.
If you are an FPGA engineer, whether you are just starting your career or have been working with programmable logic for decades, I hope you will join us.
I look forward to seeing you there!
FPGA Journal
Read about cutting edge FPGA developments, in the FPGA Horizons Journal or contribute an article.
Workshops and Webinars:
If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:
Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal
Professional PYNQ Learn how to use PYNQ in your developments
Introduction to Vivado learn how to use AMD Vivado
Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux
Arty Z7-20 Class looking at HW, SW and PetaLinux
Mastering MicroBlaze learn how to create MicroBlaze solutions
HLS Hero Workshop learn how to create High Level Synthesis based solutions
Perfecting Petalinux learn how to create and work with PetaLinux OS
Boards
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Adiuvo Embedded System Development board - Embedded System Development Board
Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.
SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces
SpaceWire RMAP Initiator - SpaceWire RMAP Initiator, digital download, AXIS & AXI4 Interfaces
SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces
Embedded System Book
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All words in this blog were written by a human.
