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Deep Dive on Altera Agilex™ 5 Architecture.

Updated: Apr 3

In our previous article, we introduced the Altera Agilex 5 FPGAs. In this article, we delve deeper into three key aspects of the Agilex 5 logic architecture: clocking, ALM (Adaptive Logic Modules), and DSP (Digital Signal Processing) elements. These form the nucleus of any solutions so it is critical we understand them in depth.


Effective Clocking

At the core of any FPGA design is the principle of synchronous operation, as such the ability to support multiple high-speed clocks within the FPGA becomes crucial. The era of using a single clock has passed; today, the average design incorporates 3 to 4 clocks (Wilson Research Group Survey 2022)This complexity necessitates the FPGA can manage several clocks efficiently across its architecture. As we will see Agilex FPGAs are optimized for high-performance, multi-clock environment.


Each Agilex device is segmented into various clock sectors, each supported by a three-level clock hierarchy. The first level delivers the clock to the sector via programmable routing from the clock source across one of 32 dedicated lines. The second level operates within the sector itself, providing 32 clocks that are routed horizontally and vertically around the sector. Clock multiplexors at each corner can be configured to manage clock distribution. Clocks enter the sector through vertical channels, facilitating the implementation of the third level of hierarchy, the row clock. Row clocks are distributed from the sector clock to each logic row and adjacent transceivers, with each row accessing six clock resources.

controllers and SERDES blocks. While fabric feeding PLLs act as fractional PLLs without the cascading capability, IO PLLs can be cascaded but only offer integer PLL functionality.


Logical ALM

The heart of the Agilex series is its Adaptive Logic Modules (ALM), which implement the logic structures captured in our designs. The ALM in Agilex is an evolution from those used in previous generations, such as the Arria 10 and Stratix 10. Central to the ALM is the 8-input adaptive LUT (Look-Up Table), which is fracturable to implement combinatorial logic features. This fracturability is crucial for synthesis tools to efficiently map logic functions that do not require all inputs. The architecture is designed around the fracturable LUT, with outputs that can be routed through a Full Adder or dual registers, offering additional flexibility by combining two full adders. Each ALM can be clocked from two sources, and when level-sensitive latches are implemented, time-borrowing capabilities are provided.

Supporting the ALM in design implementation are two internal embedded memories: the MLAB and M20K. The MLAB offers shallow memory with a block size of 640 bits, while the M20K provides 20-kilobit memories, supporting larger memory configurations.


Multi-Talented Variable Precision DSP

For applications across image and signal processing, control, and machine learning, implementing a range of mathematical operations is essential. The Agilex 5 FPGAs offer Variable Precision DSP blocks that operate in both fixed and floating-point modes. In fixed-point mode, the DSP can be configured to support precisions from 9x9 to 54x54, enabling Single Instruction Multiple Data (SIMD) operations with low precision fixed-point arithmetic. For higher precision, several DSP blocks and external adders are utilized.


The DSP supports floating-point formats FP32, FP19, FP16, and BFLOAT16. In FP16, 5 bits are reserved for the exponent and 10 bits for the mantissa, whereas BFLOAT16 allocates 8 bits for the exponent and 7 bits for the mantissa, addressing the challenges of over and underflow present in FP16 by providing a wider exponent range similar to FP32 but with reduced mantissa precision.

Notably, the DSP can also implement AI tensor block functionality, supporting Intel’s FPGA AI Suite, which is an intriguing aspect for developers.

In our next blog, we will explore the Agilex five development boards available.


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Sponsored by Altera

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