Adam TaylorJun 16, 20213 minMicroZed Chronicles: Designing in DDR to your FPGA Over the last two months, I have had several clients approach me for help regarding DDR3 / DDR3L interfaces that they have connected to...
Adam TaylorJun 2, 20215 minMicroZed Chronicles: Multi-Gigabit Transceivers One aspect of FPGA design that we haven’t really examined is multi-gigabit transceivers (MGT). These transceivers are available in many...
Adam TaylorDec 9, 20204 minMicroZed Chronicles: Implementing Safe State Machines with VivadoI thought I would examine how we can implement safe state machines when using Vivado 2020.2 and Xilinx synthesis
Adam TaylorNov 18, 20203 minMicroZed Chronicles: Using Analysis View in Vitis and Vivado One of the most useful views available in both Vivado HLS and Vitis HLS is the analysis view.