Last week we looked at IDELAY2 and ODELAY2 in 7 series IO, the selectIO which is included in 7 Series, UltraScale and UltraScale+...

In order to effectively architect solutions in Versal devices, we first need to understand how each of the elements within the device can...

Over the years, I have created MicroBlaze solutions for many Xilinx devices including Spartan-6, 7 series and up. Inserting a MicroBlaze...

One of areas I started to explore last year, but never got chance to write more than a single blog on was Versal and the VMK180...

Recently we examined Industrial Input and Output drivers in PetaLinux when using an ADC on a Pmod. Of course, all Xilinx devices also...

I have talked about my love of PYNQ for rapid prototyping of applications both commercially and for fun projects on several occasions in...

Back on the 29th September 2013, I sat down and wrote what would become the first blog in this series. It was a simple look at how to...

Last week we examined several techniques for generating non-integer clock divisions in our FPGA if no PLL was available or we couldn’t...

Modern FPGA devices really spoil us. They include PLLs, DCM, DSP etc. and a range of interfaces that significantly ease our developments....

The smart sensor IOT board we developed contains several interfaces that really require the use of an operating system to get them up...

The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped

Using Xilinx UltraFast design methodologies can offer significant benefits when implementing designs.