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Nios V Introduction

We looked at the Agilex Transceiver-SoC Development Board in the last blog. Besides the great capability of this board, one of the main reasons for obtaining it was to explore the new Nios V/m processor which is RISC-V based.

Nios II has been one of the most successful soft-core processors ever deployed and I am sure the new RISC-V-based Nios V will prove to be just as popular, if not more.


Just like with the Nios II processor, the Nios V will offer a range of configurations suitable for different applications from microcontroller and general purpose to application and Linux-capable processors. The microcontroller, which is based on the RISC-V RV32IA instruction set architecture, is the first of the Nios V processors available to developers.


For those not familiar with RISC-V, it defines an instruction set architecture, not a processor. There are three main ratified ISA: the RV32I, RV64I and RV128I. These define 32-, 64-, and 128-bit ISAs respectively. There are several extensions which can be applied to each of these base architectures. Extensions for atomic instructions (A), single and double precision floating point extensions (F and D), and extensions for integer multiplication and division (M) are among the options. Nios V is based on the 32-bit instruction set with support for atomic instructions.


To interface with external memories, both data and instruction AXI4 buses are provided. The Nios V/m provides several configuration options such as the inclusion of debug modules and interrupt controller. The rest of the Nios V is as you would expect with ALU, program control, GP and SCR registers along with timers and exception controllers.

This enables the Nios V/m to provide the developer with 0.464 DMIPs/MHZ which offers a significant increase in performance when compared to Nios II/e at 0.107 DMIPs/MHz.

Logic footprint of the Nios V/m ranges between 1300 and 1600 ALMs across different devices from Cyclone 10 to Agilex. Nios V/m provides performance between 270 MHz in a Cyclone 10 to 566 MHz in an Agilex device.


We implement the Nios V using Quartus Prime and Platform Designer which is a flow that should be familiar to those who have previously designed with Nios II devices.


The development of the software is different, however, and uses the RiscFree IDE for Intel FPGAs which is based on Ashling’s Eclipse C / C++. This provides the developer with the ability to create and debug the application. Since the Nios V/m is likely to be running on SoC-based boards which also contain Arm Corext-A53 processors, it is possible to import a HPS project and debug both applications together.


Over the next few blogs, we will explore how to implement a Nios V/m solution in Quartus Prime and then following on with the application software development in RiscFree IDE.


I will also be holding a webinar on the implementation of Nios V in early September!


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