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Intel FPGA Tool Chain Introduction

In our last look at Intel FPGAs and SoCs, we examined the range of devices and gave a brief overview of the architectures and common applications for each device family. In this blog, we are going to look at the Intel tool chain to understand the different development tools and their role in the development flow.

As you would expect, there is a range of differing tools which enable developers to create solutions at different levels of abstraction, from RTL capture to higher-level OpenCL. As such, these tools can be grouped together in terms of high-level design tools, implementation and verification, and embedded software development.

High-Level Design Tools


Intel FPGA SDK for OpenCL: OpenCL is a heterogeneous compute framework that enables portability of accelerated applications. Within the Intel framework, the Intel FPGA SDK for OpenCL enables developers to accelerate applications to leverage the parallel structures of logic available in FPGAs. The OpenCL enables developers to accelerate applications between Intel processors and FPGAs or within Intel SoCs. The Intel FPGA SDK for OpenCL enables Quartus to be called and executed under the hood, thereby abstracting the developer away from the implementation process.


Intel FPGA Add-on for oneAPI Base Toolkit: OneAPI is an open standard like OpenCL to create a standard developer experience across a range of accelerators including CPUs, GPUs, and FPGAs. This toolkit allows developers using oneAPI to target Intel Arria 10, Stratix 10 and Agilex devices. OneAPI is intended to provide a common developer experience, leveraging the SYCL language which enables definition of parallel functions that can be offloaded. OneAPI provides 10 core elements that address DNN, data analytics, threading, video processing, math, and ray tracing along with basic core elements for parallel C++ implementations.


DSP Builder: This is a model-based design tool that allows developers to leverage MathWorks Simulink. It enables the developer to implement DSP algorithms using the MathWorks Simulink environment to create an RTL implementation that can be implemented in the FPGA.


HLS Compiler: Designers can use C++ to implement individual IP functions and these functions can be compiled and optimized for performance by the HLS compiler into an RTL module. This RTL module can then be implemented within the target FPGA or SoC. Working at higher levels of abstraction enables the developer to be more efficient because both development and verification is accelerated.


Implementation, Verification and Debugging


Quartus Design Software: The main design capture and implementation software, Quartus provides developers the ability to capture the design using either RTL or IP-based design flows using Platform Designer. Once the design is captured, Quartus enables the captured design to be synthesized, fitted (place and route) and assembled (program file generation). Of course, this includes the ability to define placement and timing constraints and perform timing analysis. Quartus comes in three versions: Lite, Standard and Pro. The version you need depends on the device you are targeting. Both standard and pro versions require a paid license.


Signal Tap: Signal Tap is an in-chip logic analyzer that enables developers to understand what is occurring on the design at run time. By monitoring and trigger on signals within the FPGA, the developer can observe the design behavior and debug the design to achieve the desired behavior.


Modelsim Intel FPGA Starter Edition: Designs which are captured in Quartus require verification to ensure the design functions are as intended. To aid in this effort, Intel provides the Modelsim Intel FPGA Starter Edition which enables RTL and gate-level simulation. The Modelsim Intel FPGA Starter Edition is available in two versions: the free starter edition which is limited to 10,000 lines of code, and the standard edition which has no limitation and a faster simulation performance but requires a paid license


Embedded Development Tools


SoC Embedded Development Suite: These are Eclipse-based development environments for Intel SoC devices in the Agilex, Stratix, Arria, and Cyclone V families. Using SoCs, embedded development suite developers can create, debug, and build software applications targeting embedded Arm processor cores.


Intel NIOS II Embedded Design Suite: These are Eclipse-based development environments to create, debug, build, and deploy applications for Nios II softcore processors implemented within FPGA fabric.


Now that I have introduced the tools and the range of devices available from Intel, will get started creating our first project and say hello world using an Intel FPGA in our next blog!


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