HLS | Adiuvo Engineering

ADIUVO ENGINEERING BLOG

MicroZed Chronicles: High-Level Synthesis Interfacing

High-Level Synthesis can provide us a significant advantage when we are working in the data plane (e.g., signal / image processing and...

MicroZed Chronicles: Migrating Spartan-6 to 7 Series FPGAs and Beyond

Over the last few weeks, I have had several emails and messages about mitigating the impact of the component shortage by transitioning...

MicroZed Chronicles: Proportional Integral Derivative Controller using HLS

If I’m being honest, my university classes on control engineering were not my favorite. However, working as an engineer – and especially...

MicroZed Chronicles: The 400th Edition

Back on the 29th September 2013, I sat down and wrote what would become the first blog in this series. It was a simple look at how to...

MicroZed Chronicles: Vitis HLS and Silexica's SLX Plugin

Silexica has released a plugin for Vitis HLS 2020.2 that adds a new pragma that performs loop interchange.

Using SLX FPGA in Vitis bottom up flow

Last year, I examined SLX FPGA and used it to optimize IP Cores for implementation in Vivado looking at security and industrial algorithms.