A couple of week ago, I held several webinars on how to convert Spartan-6 designs into 7 series devices. There were several interesting...

Getting the most efficient utilization of our FPGA does not mean that we need to have the logic resources dedicated to all use cases. We...

Last week we looked at IDELAY2 and ODELAY2 in 7 series IO, the selectIO which is included in 7 Series, UltraScale and UltraScale+...

One of the greatest things about FPGAs is their IO flexibility. This flexibility allows us to recover high-speed signals, align data...

Over the years, I have created MicroBlaze solutions for many Xilinx devices including Spartan-6, 7 series and up. Inserting a MicroBlaze...

High-Level Synthesis can provide us a significant advantage when we are working in the data plane (e.g., signal / image processing and...

Embedded systems use a lot of diverse sensors from accelerometers and gyroscopes to magnetometers, vibration, temperature and humidity....

Programable logic is, of course, great for the implementation and acceleration of machine learning and artificial intelligence...

There are several FPGA use cases where a softcore processor is beneficial to the overall solution. These can include anything from...

Having an embedded Linux operating system is critical for Xilinx heterogeneous SoCs to be able to achieve their full potential. The...

On my explorations with the Kria board so far, all the imaging has been using a web camera over USB. Of course, we also can capture...

We have looked at many development boards that are based on Xilinx FPGAs and SoCs during the eight years this blog has been running....

A few weeks ago, Xilinx released Vitis AI 1.4. This was around the same time I was working on a project with the Kria SOM for a client on...

Over the years, several blogs and projects have leveraged the Vivado and Vitis ability to generate example projects. One of the most...

The first-ever MPSoC I received to work and create blogs with was an engineering sample of the UltraZed-EG in red. It worked well, but...

If I’m being honest, my university classes on control engineering were not my favorite. However, working as an engineer – and especially...

Back on the 29th September 2013, I sat down and wrote what would become the first blog in this series. It was a simple look at how to...

Last week we examined several techniques for generating non-integer clock divisions in our FPGA if no PLL was available or we couldn’t...