About the Course
FPGA’s and heterogeneous SoC’s are used in an increasing number of mission critical or high reliability applications. These applications span a diverse range from industrial, medical and scientific to defense, transportation and even space. For these devices to safely and reliability operate in an often-harsh environment, a more rigorous design approach is required. One that introduces both stricter engineering governance in the design process and design mitigation techniques
As such designing these solutions requires the designer to not only understand what techniques can be used at the logic level but also, the wider systematic, regulatory and environmental issues.
This course will therefore present the environmental challenges and what they mean to the logic designer. Along with introducing high level concepts such as SIL level, Reliability and Mean Time to Failure, attendees will also gain an understanding of the importance of engineering governance.
The focus of this course is the development of techniques which can be used in programmable logic including Clocking & Reset strategy, Triple Modular Redundancy, IO Planning, Safe State Machines and Counters, Error Correcting Codes, Single Event Effect Mitigation along with Verification strategies and metrics, formal equivalence checking, Synthesis strategies and several other advanced techniques.
Each session will complete with a Lab which will demonstrate the concepts outlined in the session. Attendees will at the completion of the course have a detailed understanding of the challenges and strategies to address the creation of mission critical systems for a wide range of applications.
• How the environment impacts our designs
• Temperature, Shock & Vibration, EMC and Radiation
• Programmatic / System level considerations.
• Different Standards 61508 / DO254 / ISO 26262
• The design life cycles
• Engineering Governance
• What is reliability & What does MTBF Mean & What impacts the MTBF
• Requirement capture & Progressive Verification
• Architectural design & Inter dependency of faults between SW and HW
• Common Cause Failures & Failure Mode & Redundancy
• Worse Case Analysis
• FPGA Design Considerations
• FPGA Development overview & Supporting Documentation
• Device Selection – OTP, FLASH, SRAM -
• Coding Style & Certified tools including
• D0254 and IEC61508 applicable standards
• Failure modes
• Different Types - Stuck At, Babbling, Data / Configuration Corruption
• Consideration during the FPGA deign process.
• Self-Test and Diagnostics
• Clocks and Rest & IO Planning & JTAG / Boundary Scan
• Safer State Machines & Counters
• Considerations for failure modes
• Design Techniques
• Synthesis Considerations
• Error Correcting Codes Communications and Memories
• Design Considerations for BRAM ECC
• Triple Modular Redundancy Local, Fine Gain and Global
• Different types of TMR and associated trade-off
• Functional Separation within the device,
• What are the objectives of isolation?
• What flow are available.
• Xilinx Isolation flow
• Single Event Effects and Configuration Corruption
• What are they within in our design – Where do they occur
• Addressing Configuration SRAM issues
• Verification & Verification Metrics & Frameworks
• Synthesis Tools
• Working with different synthesis tools for high reliability
• Include synplify and precision
• Fault Injection
• Timing Closure
• Advanced Features e.g. XADC, SysMon
• Part Stress Analysis – FPGA and Board Example
• FMECA Lab Analysis – FPGA and Board Example
• State Machine – Design and Synthesis Lab
• FPGA Coding and Code Review Lab
• MicroSemi Libero High Reliability State Machine Design
• MicroSemi Libero BRAM EDAC
• Xilinx Isolation Flow – How to segment design in logic and verify
• Xilinx TMR MicroBlaze – How to create a TMR MicroBlaze solution
• Code coverage Lab - Mentor Graphics ModelSim Required
Applicable Technologies: - These techniques outlined in this course can be applied to any FPGA technology. For reference course Xilinx Seven Series and Microsemi ProAsic 3 devices will be targeted.
Requirements: - It is expected that the attendee is an experienced FPGA designer and has familiarity with electronics and system engineering concepts.
Adam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications. Throughout his career, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites (Now Airbus Space) Payload processing group for six years and for three years he was the Chief Engineer of e2v Space Imaging, being responsible for several game changing projects.
Adam is Chartered Engineer, Senior Member of the IEEE, Fellow of the Institute of Engineering and Technology.
The team really appreciated the depth and space-specific knowledge from the Adiuvo training in Xilinx FPGAs. For me, knowing our engineers have the support of experts in the field allowing them to learn and develop at speed is fantastic -- we will be continuing to engage with Adam and the team at Adiuvo as we grow.
The course held by Adam Taylor gives a broad overview as well as technical deep dives into particular topics related to mission critical system design. The course is equally interesting for people working as system architects or as hardware / FPGA engineers. The most valuable part is that Adam enriches all covered subjects with his hands-on experience. I can recommend this course for everyone who is or might be involved with FPGA-related mission critical system design.
Dr. Theodor Hillebrand
Rheinmetall Electronics GmbH