FPGAs are great for implementing signal-processing functions such as FIR filters. The DSP elements, with their built-in multiply–accumulate capability, are ideally suited for this application. However, as with most things in FPGA design, the achievable performance depends heavily on how we architect the implementation. At a basic level, a FIR filter consists of three main elements: A delay line Multipliers to apply the coefficients An accumulator to sum the products Exactly h