I see a lot of designs across a range of industries and applications. One thing that always stands out is that designs often use complex state machines to implement features such as I²C, SPI, GPIO sequencing, etc. Often, these FSMs become unwieldy and complex, which adds to bring-up and debugging challenges. Of course, these FSMs also need to be verified in simulation and again on the board once they arrive. When I am asked to work with these interfaces in an FPGA, I often re