One of the things I have been examining lately is how I can leverage higher-performing devices, such as the Spartan UltraScale+, to implement more compact FPGA designs. There are several approaches we can take to achieve this based on the higher performance of the logic. For example, we can run AXI buses narrower but at a higher frequency; in this case we leverage the increased performance of the fabric. This works well for interfaces around our module, although the core of t