Over the last 12 months, it seems we have developed several FPGA-based boards, both as Adiuvo products and for clients. We have also been pulled into supporting FPGAs on boards that clients have designed. Often these client-designed boards have been developed on time-constrained schedules, and hence they are hoping for the best. So I am going to start off the new year talking about how we are able to reduce the technical risk in our board designs. The first thing to consider