About the Course
This course is aimed to teach people wanting to get into FPGA development the basic skill set needed to become effective designers.
Due to the length and depth of the course the delivery is split over a number of sessions and not delivered in a continuous block.
FPGA Requirements and processes flow
• What is engineering governance
• Review Processes / Check Lists / Gate Reviews
• Example Review Stages e.g. SRR / PDR, CDR, etc
• Standards we might work with
• Do254 / iec61508 / iso26262
• Safety integrity Level
• Failure Space
• System engineering V Model
• Challenges of environments – Temperature, Vibration, Radiation, EMC
Systems Engineering
• What makes a clear requirement
• Levels of Requirement
• Cross Referencing
• Engineering Budgets
• Verification Strategies
Architecting the FPGA how to approach the architecture of the device
Key elements of FPGA Architecture
• IO planning
• Clocking
Architectures and considerations
• Global, Regional, Source Synchronous Clocks
• IP Blocks, Reuse, standardisation
• Interconnect technology AXI, APB, Wishbone
• External interfaces I2C, SPI, UART
• Bridging external to internal interfaces and technology
• Complex memories e.g DDR3, DDR4
• How to define architectures & registers - Using SysML
• Clock Domain Planning and safe CDC analysis
• Documenting the architecture
• IO – Standards, Drives, Pulls
• Clocks
• Memory Map
Documentation for modules required to be developed
• IO
• Clocking
• Registers
• Error conditions and failure cases
Verification strategies
• Planning for verification
• Verification Documentation
• Commonly used frameworks
• UVM
• UVVM / OSVM
• Cocotb
• Corner cases and boundary conditions
• Constrained random
• Code Coverage
• Self-Checking Test Benches
• Independence in verification
Constraints
• What is the purpose of constraints – Physical and timing
• Where do we use constraints
• Synthesis – Control Optimisation etc
• Placement – Control physical placement and location
• Advanced e.g. Partial Reconfiguration / Isolation Flow
FPGA initial design skills
• How to design FPGA using VHDL
• Leverage Packages / Libraries / procedures and functions
• FSM Styles – Single Process, Safe State Machines,
• Counters – Coding for performance, safety
• Pipelining,
• Working with BRAM and DSP
FPGA advanced skills
• Clock domain crossing,
• Coding for security / Reliability –
• FSM,
• SECDED on Memories,
• Isolation flow, TMR,
• FPGA Mathematics
• IO structures – I/OSERDES, DDR etc
IP Usage
• When and where is it appropriate to IP
• How to integrate IP in your design to enable portability
Softcore processors -
• Creation of MicroBlaze solution in FPGA
• Debugging MicroBlaze
• Integrating with IP
• Real Time, Interrupt Driven Processing
• Boot and Configuration Options
System on Chip Design
• Creation of Zynq / MPSoC based systems
• Basic intro to SoC system creation
• FPGA /SW integrations and communication
• Embedded Linux
• Debugging – Cross Probing
Timing Analysis
• What is STA
• How to find failing paths
• Correction of issues
• Routing vs Logic
• How to analyse IO timing
Debugging on Hardware
• Considerations for board bring up
• Debug methodology and how to debug a design
• Use of ILA
Online Dates for 2024
Feb - FPGA Development - Monday - Friday - 12th to the 16th
April - FPGA Development - Monday - Friday 15th to 19th
June - FPGA Development - Monday - Friday 17th to 21st
August - FPGA Development - Monday - Friday - 12th - 16th
October - FPGA Development - Monday - Friday 14th - 18th
If you are interested, in the course email training@adiuvoengineering.com
Your Instructor
Adam Taylor
Adam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications. Throughout his career, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites (Now Airbus Space) Payload processing group for six years and for three years he was the Chief Engineer of e2v Space Imaging, being responsible for several game changing projects. Adam is Chartered Engineer, Senior Member of the IEEE, Fellow of the Institute of Engineering and Technology.
Recommendations
The FPGA training course I did was online, it was very well presented by Adam Taylor and followed a logical progression that was easy to understand. Adam was more than willing to answer questions. The exercises were at a good level, and also followed a logical process.
I learned a lot during the course and would recommend the course to anyone with some level of understanding with FPGAs who wants to increase the knowledge and experience of the tool chain and processes for development.
Design Engineer - Space Systems
The course covers a good selection of subjects on FPGA for newcomers to the industry. As well as explaining the basics of how FPGAs work and their purpose, it also gives an idea of the more advanced techniques that can be used in their development. Even people with some experience could get some ideas from here
Head of Digital Systems - Communications